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研究生： 張家賢
Jia-Xian Chang
論文名稱： 一個2V 5GHz CMOS非整數頻率合成器與和差調變器設計
A 2V 5GHz CMOS Fractional-N Frequency Synthesizer with a ΔΣ Modulator
指導教授： 陳巍仁
Wei-Zen Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 89
語文別： 中文
論文頁數： 46
中文關鍵詞： 非整數頻率合成器 、和差調變器 、多係數除頻器
外文關鍵詞： Fractional-N Frequency Synthesizer, ΔΣ Modulator, Multi-Modulus Frequency Divider
相關次數： 點閱：11  下載：0 
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    • 　　頻率合成器(Frequency Synthesizer)是通訊系統射頻前端的一個重要元件。在以鎖相迴路(Phase-Locked Loops)為基礎的設計上，會遭遇頻率解析度(Frequency Resolution)、轉換速度(Switching Speed)與相位雜訊(Phase Noise)等問題。
    　　本論文採用和差調變器(Sigma-Delta Modulator)技術的非整數頻率合成器，可同時達到好的頻率解析度、快速的轉換速度與低的相位雜訊。包含的元件有相位頻率偵測器(Phase Frequency Detector)、電荷充放器(Charge Pump)、迴路濾波器(Loop Filter)、壓控振盪器(Voltage Controlled Oscillator)、倍頻器(Frequency Doubler)、多係數除頻器(Multi-Modulus Frequency Divider)與二位元三階和差調變器(2-bit 3rd Order Sigma-Delta Modulator)。
    　　在晶片設計上，針對5GHz的ISM頻帶設計一2V 5GHz的頻率合成器，以0.35μm 1P4M CMOS製程完成。在2V的操作電壓下，功率消耗為80mW，晶片面積為3210μm×2410μm。


    This thesis proposes a single chip CMOS fractional-N frequency synthesizer using sigma-delta modulator. It can achieve fine frequency resolution, fast switching speed and low phase noise simultaneously. The frequency synthesizer is composed of a phase frequency detector, a charge pump, a loop filter, a VCO, a frequency doubler, a multi-modulus frequency divider and a 2-bit 3rd order sigma-delta modulator.
    The design of the 2V 5GHz frequency synthesizer aims at the 5GHz ISM band. Implemented in TSMC 0.35μm 1P4M CMOS technology, the circuit consumes 80mW from 2V supply and occupies chip size of
    3210μm×2410μm.

    第一章簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1 　1.1　研究動機‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 1 　1.2　組織架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 2 第二章鎖相迴路‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 3 　2.1　簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 3 　2.2　鎖相迴路的雜訊‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 4 　2.3　整數鎖相迴路‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 6 　2.4　非整數鎖相迴路‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 7 第三章和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 10 　3.1　簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 10 　3.2　和差調變器架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 10 　3.3　低階和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 11 　　3.3.1　一階和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧12 　　3.3.2　二階和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧13 　3.4　高階和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 14 　3.5　單級和差調變器架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 15 　3.6　多位元和差調變器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 16 　3.7　諧波與加入雜訊‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 16 第四章鎖相迴路電路設計‧‧‧‧‧‧‧‧‧‧‧‧‧ 18 　4.1　簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 18 　4.2　相位頻率偵測器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 19 　4.3　電荷充放器與迴路濾波器‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 20 　4.4　壓控振盪器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 21 　4.5　倍頻器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 22 　4.6　多係數除頻器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 24 　　4.6.1　除頻器簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 24 　　4.6.2　前置除頻器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 25 　　4.6.3　可程式計數器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 28 　　4.6.4　屏蔽計數器‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 30 第五章和差調變器電路設計‧‧‧‧‧‧‧‧‧‧‧‧ 32 　5.1　簡介‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 32 　5.2　和差調變器架構‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 32 　5.3　穩定性分析‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 34 　5.4　和差調變器電路‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 35 　5.5　總結‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 39 第六章佈局與量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 40 　6.1　佈局‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 40 　6.2　量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 42 　　6.2.1　多係數除頻器量測結果‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 42 　　6.2.2　壓控振盪器與倍頻器量測結果‧‧‧‧‧‧‧‧‧‧‧ 42 第七章結論‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧ 44 參考文獻‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧‧45

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