隨著無線通訊技術的進步，5G已經開始蓬勃發展，並期望能應用在物聯網與車用電子甚至是遠端手術等，對於資料的傳輸速度以及資料量的需求越來越高。因此我們希望能開發出符合此需求的收發機，並且完成實際的應用。為了實現高傳輸速度與高資料量的收發機模組，透過多路平行處理架構同時處理多筆資料，以硬體資源提高資料處理速度，最終利用FPGA實現實際的訊號收發。
在本論文中，我們設計收發機硬體架構並以Verilog硬體描述語言實現，收發機規格參考LTE DownLink架構下的OFDM調變系統，並搭配上DVB-T架構之通道編解碼規格進行修改與擴充。以上述規格開發出傳輸速度與資料量高的可靠收發機模組，並在RFSoC平台實現與使用號角天線及升降頻模組達成毫米波段之收發，最後展示其在中頻與毫米波段不同通道下的結果。
本論文另一重點是RFSoC與毫米波升降頻器開發板的使用，簡單講述如何利用PYNQ開發RFSoC並且實現RFSoC與電腦間的資料傳輸，還有RFSoC內各項基本矽智財的使用與其參數說明及設定，以及毫米波升降頻器開發板的使用與參數設定。

With the advancement of wireless communication technology, 5G has begun to flourish, and it is expected to be applied to the Internet of Things, automotive electronics and even remote surgery. The demand for transmission speed and data quantity is getting higher and higher. In order to achieve high transmission speed and high data quantity, we use parallel processing architecture to process multiple data at the same time. Increase data processing spend by hardware resources. Finally, complete the actual signal sending and receiving by FPGA.
Designed with Verilog hardware description language in the hardware. The transceiver module refers to the OFDM modulation system under the LTE DownLink architecture along with the channel decoding specification under the DVB-T architecture to modify and expand. Develop the reliable transceiver module with high transmission speed and large data quantity, and finally completed it on the RFSoC platform. Use up/down converter and horn antenna to achieve transmission in the millimeter wave band. Eventually show the result of the IF and millimeter wave bands.
Another focus of this thesis is the use of RFSoC and millimeter wave frequency converter development board. Briefly describe how to use PYNQ to develop RFSoC and achieve data transmission between RFSoC and computer. Descript the parameters and settings of basic silicon intellectual property of RFSoC and the settings of millimeter wave frequency converter development board.

[1] Chang-Yueh. Liu, “Design and Implementation of Wideband OFDM Transceiver with SDR Platform” National Central University, Master’s thesis, Dec. 2019.
[2] Tzu-Chun. Liu, “Implementation of High Throughput Codec for Wideband OFDM Tranceiver with SDR Platform” National Central University, Master’s thesis, Dec. 2019.
[3] Guan-Ciou Huang “Implementation of Wideband OFDM mmWave Transceiver with RFSoC Platform” National Central University Master’s thesis, Oct, 2020.
[4] C.H. Kuo, “Design and Implementation of Viterbi Decoder for Multi-Rate Convolutional Code in DVB-T System” National Central University, Master’s thesis, Jul. 2010.
[5] Yih-Min Chen, Hsin-Yin Wu, and Mong-Yo Lu. “Decision-directed polynomial model-based channel estimation for ofdm systems with scattered-pilots,” in ITS Telecommunications (ITST), 2012 12th International Conference on, pages 748-752. Nov, 2012.
[6] Jae-Sun Han, Tae-Jin Kim, Chanho Lee, “High performance Viterbi decoder using modified register exchange methods,” in 2004 IEEE International Symposium on Circuits and Systems, Vol.3, Page(s):III – 553-6, May 2004
[7] D. A. F. Ei-Dib and M. I. Elmasry, “Low-power register-exchange Viterbi decoder for high-speed wireless communications,” IEEE ISCAS, Vol. 5, pp. V737~740, May. 2002.
[8] Feygin, G.; Gulak, P, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoder,” Communications, IEEE Trans. On Communications, Vol 41, Issue 3, Page(s):425~429, March 1993
[9] T. K. Truong, M. –T. Shih, I. S. Reed, and E. H. Satorius, “ A VLSI design for a trace-back Viterbi decoder,” IEEE Trans. on Communications, Vol. 40, No.3, pp.616~624, Mar. 1992.
[10] Ivan M. Onyszchuk, “Truncational Length for Viterbi Decoding,” IEEE Trans. On Communication, Vol.COM-39, pp.1023~1026, July 1991.
[11] C. B. Shung, P. H. Siegel, G. Ungerboeck, and H. K. Thapar, “VLSI architectures for metric normalization in the Viterbi algorithm,” IEEE ICC, Vol. 4, pp.1723-1728, Apr.1990.
[12] F. Weng, C. Yin, and T. Luo,” Channel estimation for the downlink of 3gpp lte systems,” in Network Infrastructure and Digital Content, 2010 2nd IEEE International Conference on, pages. 1042-1046, Spet. 2010.
[13] Q. Wang, C. Mehlfuhrer, and M. Rupp, “Carrier frequency synchronization in the downlink of 3gpp lte,” in 21st Annual IEEE International Symposium on Personal, Indoor and Mobile Radio Communications, pages. 939–944, 2010.
[14] A. Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” in Acoustics, Speech, and Signal Pro- cessing, IEEE International Conference on ICASSP’80, vol. 5, pages. 964–967, IEEE, 1980.
[15] J. E. Volder, “The cordic trigonometric computing technique,” IRE Transac- tions on Electronic Computers, no. 3, pages. 330–334, 1959.
[16] M.-X. Chang and Y. T. Su, “Model-based channel estimation for OFDM signals in Rayleigh fading,” IEEE Transactions on Communications, vol. 50, no. 4, pp. 540-544, 2002.
[17] H. G. Myung, J. Lim, and D. J. Goodman, “Peak-to-average power ratio of single carrier fdma signals with pulse shaping,” in Personal, Indoor and MobileRadio Communications, 2006 IEEE 17th International Symposium on, pp. 1-5, 2006.
[18] A. Sohl, T. Frank, and A. Klein, “Channel estimation for dft precoded ofdma with blockwise and interleaved subcarrier allocation,”in Proc. International OFDM Workshop 2006
[19] X. Wang and K. R. Liu, “Channel estimation for multicarrier modulation sys-tems using a time-frequency polynomial model," IEEE transactions on commu-nications, vol. 50, no. 7, pp. 1045-1048, 2002.
[20] Xilinx(2018, Decdmber 5). Zynq UltraAcale+ RFSoC RF Data Converter Evaluation Tool(ZCU111) User Guide. Retrieved from
https://www.xilinx.com/support/documentation/boards_and_kits/zcu111/ug1271-zcu111-eval-bd.pdf
[21] Xilinx(2018, April 17). Zynq UltraScale+ RFSoC RF Data Converter 2.0 LogiCORE IP Product Guide. Retrieved from
https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_0/pg269-rf-data-converter.pdf
[22] Arm Developer. AMBA 4 AXI4-Stream Protocol Specification. Retrieved from
https://developer.arm.com/documentation/ihi0051/a?lang=en
[23] Xilinx. PYNQ:PYTHON PRODUCTIVITY. Rertieved from
http://www.pynq.io/
[24] ANALOG DEVICES. ADF4372: Microwave Wideband Synthesizer with Integrated VCO. Retrieved from
https://www.analog.com/en/products/adf4372.html
[25] ANALOG DEVICES. ADNV1013: 24GHz to 44GHz, Wideband, Microwave Upconverter. Retrieved from
https://www.analog.com/en/products/admv1013.html
[26] ANALOG DEVICES. ADMV1014: 24GHz to 44GHz, Widebnd, Microwave Downconverter. Retrieved from
https://www.analog.com/en/products/admv1014.html
[27] A-INFO. Standard Gain Horn Antenna: LB-28-20-C-XX. Retrieved from
http://www.ainfoinc.com.cn/en/pro_pdf/new_products/antenna/Standard%20Gain%20Horn%20Antenna/tr_LB-28-20.pdf
[28] K. Sobaihi, A. Hammoudeh, D. Scammell, “Automatic Gain Control on FPGA for Software-Defined Radios,” in London, UK, 2012 Wireless Telecommunications Symposium, IEEE Aug. 2012.