本論文自我校正的方法是為了克服系統內建自我測試電路中，因製程飄移的誤差所提出解決的方法。利用在同一晶片上的數位訊號處理器或是微處理器，來進行測試結果的資料分析。所提出的方法只需藉由四個電阻與一個電容，純被動元件即可。這是非常容易控制與分析的。我們提出了兩種方法，一個是統計的方法，另一種為曲線比較的方式。利用離散元件來實際組裝硬體電路，模擬內建自我測試電路的類比數位轉換器。實驗結果驗證了此方法的可能性。所提出的兩種量測方法與IEEE1057測試方法的誤差均小於2LSB。

A self calibrated BIST methodology is proposed to overcome the process variation of the BIST circuitry. The on-chip digital signal processor or micro processor can be used as data analyzer for test result analysis. The proposed methodology can be generated via passive components only, four resistors and one capacitor. It is very ease to control and analysis. Two test methods are proposed, one by statistical analysis and another by curve fitting. Test hardware is built by discrete components to emulate the ADC BIST circuitry. Experimental results verify the feasibility of the methodology. The differences between both methods with IEEE Std.1057 method are within 2LSB for a 12-bit ADC.

[1] J.L Huang, C.K. Ong and K.T. Cheng, “A BIST scheme for on-chip ADC and DAC testing,” Proc. Design Automation and Test in Europe, 2000, pp.216-220.
[2] Y.C. Wen and K.J. Lee, “An on Chip ADC Test Structure,” Proc. Design Automation and Test in Europe 2000, pp.221-225.
[3] F. Azais, S. Bernard, Y. Bertrand, and M. Renovell, “Implementation of a linear histogram BIST for ADCs,” Proc. Design, Automation and Test in Europe, 2001, pp. 590-595.
[4] M. Renovell, F. Azais, S. Bernard, and Y. Bertrand, “Hardware Resource Minimization for Histogram-Based ADC BIST,” Proc. VLSI Test Symposium, 2000, pp.247-252.
[5] M.F. Toner and G.W. Roberts, “A BIST scheme for an SNR test of a sigma-delta ADC,” Proc. Int''l test Conference, 1993, pp. 805-814.
[6] M.F. Toner and G.W. Roberts, “A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a sigma-delta ADC,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal, Vol. 43 No. 8, 1996, pp. 608-613.
[7] S.K. Sunter and N. Nagi, “Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST,” IEEE Int''l Test Conference, 1997, pp.389-395.
[8] E.J Peralias, A. Rueda, J.L. Huertas, “Structural testing of pipelined analog to digital converters,” Proc. IEEE Int''l Symp. On Circuits and Systems, 2001, vol. 1, pp. 436-439.
[9] L. Schnell, Technology of Electrical Measurements, John Wiley and Sons, 1993.
[10] IEEE Std. 1057-1994, IEEE Standard for Digitizing Waveform Recorders, IEEE 1994.
[11] Kuyel, T., “Linearity testing issues of analog to digital converters,” Test Conference, 1999. Proceedings. International, pp. 747-756, 1999
[12] Larrabee, J.H., Hummels, D.M., and Irons, F.H., “ADC compensation using a sinewave histogram method,” Instrumentation and Measurement Technology Conference, 1997. IMTC/97. Proceedings. Sensing, Processing, Networking., Vol.1, pp. 628-631, 1997
[13] Bellan D., Brandolini A., and Gandelli A., “ADC nonlinearity and harmonic distortion in FFT Test,” Instrumentation and Measurement Technology Conference, 1998. IMTC/98. Conference Proceedings. IEEE Volume: 2, 1998, pp. 1233-1238 vol. 2
[14] Mielke, J.A., “Frequency domain testing of ADCs,” IEEE Design & Test of Computers, Vol. 13, pp. 64-69, 1996
[15] Ben-Hamida N., Ayari, B., and Kaminska B, “Testing of Embedded A/D Converters in Mixed-Signal Circuit”, Computer Design: VLSI in Computers and Processors, 1996. ICCD ’96. Proceedings., 1996 IEEE International Conference on, 1996, pp. 135-136
[16] Mark Burns and Gordon W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, 2001.