本論文主要討論使用注入鎖定技術之微波及毫米波低相位雜訊訊號源積體電路的研究。首先，提出一個利用調整正負阻比值而達到高輸出功率及高效率的24-GHz功率振盪器，實現於砷化鎵0.15微米假晶高電子遷移率電晶體 (PHEMT) 製程。另外，此電路也可當作一個相位位移器使用。量測最大輸出功率為21.3 dBm而效率最高達41.7%。利用相同的方法，進一步提出一個高效率的U-band功率振盪器，實現於砷化鎵0.1微米假晶高電子遷移率電晶體 (PHEMT) 製程。提出的功率振盪器與最近所發表的功率振盪器互相比較，展現高效率及高功率輸出等優點。
接著，第三章為兩個K頻段全積體化的多相位壓控振盪器，第一個是使用穩懋砷化鎵材質之異質接面雙極性電晶體和假晶高電子遷移率電晶體製程的並聯耦合四相位壓控振盪器，另一個則是使用90奈米金屬氧化半導體製程實現的八相位壓控振盪器，採用串連耦合形式並且使用變壓器回授及電流再利用的架構。此外，本論文中也針對如何直接量測多相位壓控振盪器之振幅及相位誤差作了討論。此二電路的量測結果與先前所發表的多相位壓控振盪器相比，擁有低振幅低相位誤差的優點。
第四章使用延遲鎖定迴路自我對準注入的技術，實現一個次諧波注入鎖定鎖相迴路。藉由此次提出的架構，讓注入訊號與壓控振盪器的輸出相位隨環境變異可以自動的對準，進一步的降低抖動(jitter)以及改善鎖相迴路的中心頻雜訊。在操作頻率為2.3 GHz及偏移中心頻為1 MHz時，量測次諧波注入鎖定鎖相迴路之相位雜訊為-123.1 dBc/Hz，均方根值(rms)抖動為356 fs。
最後，我們總結這篇論文所提出的研究成果於第五章。

Design and analysis of low phase noise signal source integrated circuits using injection-locked technique is presented in this dissertation. A 24-GHz high output power and high efficiency power oscillator (POSC) is proposed using a 0.15-µm GaAs PHEMT process in Chapter 2. It also can be used as an active injection-locked phase shifter. By tuning the ratio between the input resistance and load resistance, the proposed POSC achieves a maximum output power of 21.3 dBm and a maximum efficiency 32%. Besides, using the same way, a U-band high efficiency POSC using a 0.1-µm GaAs PHEMT process is also presented. These two works demonstrate good figure-of-merit (FOM) among all the reported fully integrated POSCs.
In Chapter 3, two fully integrated K-band multi-phase voltage-controlled oscillators are presented. First one is a parallel-coupled quadrature-phase voltage-controlled oscillator (P-QVCO) using a 0.5-µm BiFET process. The second is an eight-phase VCO with current-reused configuration and transformer-feedback using a standard bulk 90-nm COMS process. Besides, the characterization of the amplitude and phase errors for the multi-phase VCO is successfully demonstrated using the proposed innovative method. As compared with the previously reported state-of-the-art multi-phase VCOs, these works feature low phase and amplitude errors.
A 2.5-GHz SILPLL with delay-locked loop (DLL) self-aligned injection using 65-nm CMOS technology is presented in Chapter 4. With the proposed innovative topology, the phase between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator (SILVCO) in the PLL can be dynamically aligned to minimize the jitter over the variation. The in-band phase noise of the SILPLL can be significantly improved using the SIL technique. As the operation frequency is 2.3 GHz, the measured phase noise of the proposed SILPLL with self-aligned injection is -123.1 dBc/Hz at 1 MHz offset with a rms jitter of 356 fs.
Finally, we summarize the conclusion in Chapter 5.

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