DVB-S2 接收器之FPGA實現｜國立中央大學博碩士論文系統

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研究生：	羅豫碁 Yu-chi Lo
論文名稱：	DVB-S2 接收器之FPGA實現 Design and Implementation of DVB-S2 Receiver with FPGA
指導教授：	陳逸民 Yih-min Chen
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 通訊工程學系 Department of Communication Engineering
論文出版年：	2015
畢業學年度：	104
語文別：	中文
論文頁數：	104
中文關鍵詞：	第二代數位電視廣播、符碼同步、載波同步、Frame同步、軟式決定解碼
外文關鍵詞：	DVB-S2, Symbol Synchronization, Carrier Synchronization, Frame Synchronization, Soft-Decision
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第二代數位衛星廣播 (DVB-S2) 為新一代的數位衛星廣播標準以提升相較於 DVB-S之傳輸量。與DVB-S相比，DVB-S2可提供除QPSK外的多種具有更高頻帶利用率的調製方式，如8PSK、16APSK、32APSK。減少了幅度變化，更能適應線性特性相對不好的衛星傳輸通道。

本論文研究內容以FPGA硬體架構設計與實現DVB-S2內部接收端，包含符碼同步，載波同步，Frame同步以及供給外在接收模組的軟式決策(Soft-Decision)解碼模組。符碼同步採用內插器，以消除時序偏移並進行同步取樣。載波同步則是以固定星座圖計算出相位和頻率偏移，進行回復處理。而Frame同步是經由已知的SOF (Start Of Frame)完成相關器，求出起始位置已截取出正確的Frame範圍，並避免相位的不明確性。而在軟式決定解碼部份，本論文運用了負數旋轉，以對事先計算出的硬式決策(Hard-Decision)邊界，求出與邊界的距離，而得知訊號點的數概似值比(Log Likelihood Ratio, LLR)，以簡化計算的複雜度。

Digital Video Broadcasting - Satellite - Second Generation(DVB-S2) is a digital television broadcast standard that has been designed as a successor for the popular DVB-S system. In comparison with DVB-S, besides QPSK, DVB include enhanced modulation schemes up to 8PSK, 16APSK and 32APSK, which increase of available bitrate over the same satellite transponder bandwidth. Otherwise, it can reduce the phase offset and have a good performance in channel interference.

The reaserch topic of this thesis is on the hardware architecture design and realization of the DVB-S2 inner receiver with FPGA, Including Symbol Synchronization, Carrier Synchronization and Frame Synchronization, and Soft-Decision module which supplys Log likelihood Ratio (LLR) to outer receiver. The Symbol Synchronization uses interpolator to solve timing offset and do the sampling process. The Carrier Synchronization uses the ideal constellation of QPSK, 8PSK, 16APSK and 32APSK to caculate the phase and frequency offset of the input signal.The frame Synchronization uses the SOF(Start of Frame) which is known data to design a correlator, and caculate the beginning of frame. Then, we can catch the frame we need and avoid the ambiguous of phase. About the Soft-Decision, in this thesis I use the complex rotaion to caculate the distance of the boundary of Hard-decision I had caculate in accurate method, and use the distance as the LLR to simplify the caculate.

中文摘要.............................................................................................................. i
ABSTRACT ......................................................................................................... ii
謝誌...................................................................................................................... iii
目錄...................................................................................................................... iv
圖目錄.................................................................................................................. vii
表目錄.................................................................................................................. xi
一、緒論.............................................................................................................. 1
1 研究動機與背景. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 章節簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
二、DVB-S2規格簡介......................................................................................... 3
1 DVB-S2傳送端流程. . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Frame 架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 FEC frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 PL frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Frame內部建構運作. . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Bit Interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 PL Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 QPSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 8PSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 16PSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 32APSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
iv
三、DVB-S2 內部接收端系統原理.................................................................... 14
1 接收端流程架構. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.1 接收端架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 接收端訊號模型. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 再取樣(Resampling) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 費洛內插器(Farrow Interpolator) . . . . . . . . . . . . . . . . . . 17
2.2 Cubic Lagrange Interpolator . . . . . . . . . . . . . . . . . . . . . 19
3 匹配濾波器(Matched Filter) . . . . . . . . . . . . . . . . . . . . . 20
4 符碼同步(Symbol Synchronization) . . . . . . . . . . . . . . . . . 22
4.1 符碼同步原理架構. . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 載波同步(Carrier Synchronization) . . . . . . . . . . . . . . . . . 26
5.1 DVB-S2訊號規格Hard-Decision . . . . . . . . . . . . . . . . . . . 27
5.2 載波同步原理架構. . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Frame同步. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 相關器(correlator) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2 Descarambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
四、軟式決策解碼.............................................................................................. 39
1 理想算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.1 各星座圖Hard-Decision邊界. . . . . . . . . . . . . . . . . . . . . 41
2 簡化計算. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1 QPSK的LLR計算. . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2 兩星座點離邊界非等距離. . . . . . . . . . . . . . . . . . . . . . 50
2.3 最近邊界算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4 邊界距離算法. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.5 8PSK邊界距離算法. . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.6 與精確值比較. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
五、硬體架構實現.............................................................................................. 58
1 符碼同步模組. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
1.1 Farrow Interpolater . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2 Timing Error Detector . . . . . . . . . . . . . . . . . . . . . . . . . 63
v
2 載波同步模組. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1 Decision-Directed Phase-Error Estimator . . . . . . . . . . . . . . 65
2.2 Loop lter(carrier synchronization) . . . . . . . . . . . . . . . . . . 66
3 Frame同步模組. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.1 相關器(Correlator) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.2 First and second peak search模組. . . . . . . . . . . . . . . . . . 68
4 Soft-Decision模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1 8PSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2 16APSK和32APSK . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 Bit Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
六、FPGA實現結果........................................................................................... 78
1 硬體使用資源. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2 硬體測試結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
七、結論與未來展望.......................................................................................... 87
參考文獻..............................................................................................................88
                                

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