由於人們對於影像解析度的要求越來越高，造成影像資料量隨之增加，但衛星至基地台間的傳輸通道容量有限，因此必須將巨量的資料進行壓縮再回傳，本論文設計了指數項延伸型區塊可調式區塊浮點數量化器(Tunable Block Floating-Point Quantizer with Fractional Exponent)來壓縮訊號並保持良好的影像解析度，傳統的BFPQ利用指數項來涵蓋輸入訊號的範圍，在每個區塊中會選擇一個最大值，並計算其指數項供其他訊號使用，利用其量化邊界可得到量化後結果，透過量化代表值可得到均方誤差(Mean Square Error, MSE)，誤差型態分為量化誤差及飽和誤差，配合著輸入訊號能量可計算出信號量化雜訊比(Signal-to-Quantization-Noise Ratio, SQNR)來評估效能，在區塊較大時傳統式方法的量化誤差增長速度大於飽和誤差造成效能低落，因此我們提出的可調式方法改變獲取指數項時的量化邊界，使得量化誤差及飽和誤差可以得到平衡以提升系統效能，我們的系統中，可將ADC所輸入的訊號從14bits壓縮成2、3、4、6或8bits輸出，區塊可設定成8、16或32，指數項具有3位元，指數延伸項則是區塊大小與輸出的位元長度有2位元或3位元的設定。在硬體設計方面我們提出的方法會比傳統式的多出一個乘法器來做邊界的調整，我們使用Xilinx Virtex-7系列的FPGA進行硬體設計及驗證，為了追求更高的操作頻率，我們將平行處理及管線化(Pipeline)的技巧加入設計當中，實際測量下的操作頻率可達到200MHz，由於四路平行處理，可支援ADC取樣率達800MHz，另一方面也使用了台積電所提供的40奈米製程進行實作，操作時脈可達250 MHz，支援1000MHz 取樣率之ADC，在1V時，功耗為7.85mW，由此可觀察本設計有不錯的硬體使用效率。

As the requirements for synthetic aperture radar (SAR) image resolution are get-ting higher and higher, the sampling frequency and output word-length of ADC keep growing. Both result in the increase of output data quantity. However, the data rate of the link channel between satellites and ground stations is limited. Therefore, the huge amounts of data must be compressed. In this paper, a tunable block floating-point quantizer with fractional exponent is designed to compress the SAR signals so as to maintain good quality. Conventional BFPQ uses exponent to cover the wide dy-namic range of input signals. The exponent of the maximum value of each block is shared among the data in the block and then the threshold is used to derive the quantized results. The representative values in each quantization interval are em-ployed to calculate the error. The error component can be divided into quantization error and saturation error. The performance is evaluated by signal to quantization noise ratio. The proposed tunable BFPQ enlarges the thresholds for exponent and fractional exponent judgement, which can balance the quantization error and the saturation error and thus improve system performance, especially for signals of a large block size. The worlength of the fractional exponent can also be reduced. In our system, the input signal by the ADC can be compressed from 14bits to 2, 3, 4, 6 or 8bits output, and the block size can be set as 8, 16 or 32. In the hardware design, only an extra multiplier is incurred to realize the proposed technique. We use the Xilinx Virtex-7 series of FPGA for verification. In order to pursue higher operating frequen-cy, parallel processing and pipeline techniques are adopted. The measured clock fre-quency reaches 200MHz and can support interleaved ADC with sampling frequency 800MHz. The hardware is also implemented in 40nm CMOS process. The clock fre-quency can be driven up to 250MHz and the power consumption is 7.8mW at 1V supply voltage.

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