在現今常見的類比積體電路中，如類比/數位轉換器及切換式電容電路，效能的關鍵樞鈕，常常在於其電路中電容陣列的電容比例精確度，而如何實現其精確的電容比例在目前仍是一項很重要的議題。在類比積體電路製造過程中，常常會發生主要兩類的不匹配現象：系統性不匹配和隨機性不匹配。系統性不匹配形成的主要原因，常見為不對稱的元件擺放方式，造成氧化層厚度的變動，間而影響到了製程梯度，產生了梯度誤差。而隨機性不匹配常常是因類比電路在製造過程中，自然界中相關的隨機變動，影響到了多項製程參數而造成了隨機性不匹配，而不匹配的現象也影響到了電路效能及穩定性。
目前已有許多相關的研究在試圖找出如何同時解決兩者不匹配的狀況，並獲得最佳的電容布局，但泰半方法都得犧牲許多運算時間來換得更好的結果。本篇論文旨在發展一平行基因演算法，使其符合求取最佳電容布局結果的相關條件再加上相對應的改良式基因操作，最後再輔以現代社會廣泛普遍的多核心系統，讓程式架構、平行處理及多核心系統等效能因子能融為一個整體，讓整個運算效能能以倍數來成長。而經過實驗後，結果也顯示了相對於啟發式演算法、模擬退火法，甚或是數學分析法，我們所發展的平行基因演算法可以在更短的時間內產生出品質參數接近或更好的電容布局，在電容布局研究的耗時問題解決上又大大的邁出了一步。

In the common analog integrated circuits today, such as an analog-to-digital converter and switched-capacitor circuit, the critical point of its performance often depends on the high accuracy capacitance ratios. And how to implement the accurate capacitance ratios is still an important issue so far. During the manufacturing process for analog integrated circuits, there are two major types of capacitor mismatches: system mismatch and random mismatch. Usually, the main cause of system mismatch is the unsymmetrical device placement and results in the variation of oxide thickness which affects the process gradient and causes the gradient errors. And Random mismatch often appears with the relatedly random variation in nature which affects most of process parameters during the analog integrated circuits manufacturing process. The mismatch not only reduces the circuit performance but also make the circuit unstable.
There are many related researches to find out how to solve these two kinds of mismatch issues and try to acquire the best capacitors placement up to now, but most of them need much runtime to get the better results. Because of the reasons mentioned above, this thesis aims to develop the parallel genetic algorithm to obtain the best capacitors placement by satisfying the design requirements and going with the corresponding genetic operations. At last, we work the algorithm on the multi-core system to double the operational speed. The experimental results show that our method can generate the better capacitors placement with shorter runtime and make great progress in solving the time-consuming problem of capacitor placement.

[1]Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, and Soon-Jyh Chang, “Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits ,” Proc. International Conference on Computer-Aided Design(ICCAD), pp. 635-642, 2012.
[2]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 12, pp. 1789-1802, December, 2012.
[3]Jwu-E Chen, Pei-Wen Luo, and Chin-Long Wey, “Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio,” Proc. International Symposium on Quality Electronic Design (ISQED), pp. 179-184, 2009.
[4]Jwu-E. Chen, Pei-Wen Luo, and Chin-Long Wey, “Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 2, pp. 313-318, February, 2010.
[5]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, “Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” Proc. Design Automation Conference (DAC), pp. 528-533, 2011.
[6]Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, and Wen-Ching Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 2097-2101, November, 2008.
[7]Hiroo Masuda, Shin-Ichi Ohkawa, Atsushi Kurokawa, and Masakazu Aoki, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes,” Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 593-599, 2005.
[8]DiaaEldin Sayed and Mohamed Dessouky, “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proc. Design, Automation and Test in Europe (DATE), pp. 576-580, 2002.
[9]Jyn-Bang Shyu, Gabor C. Temes, and Francois Krummenacher, “Random Error Effects in Matched MOS Capacitors and Current Sources,” IEEE Journal of Solid-State Circuits (JSSC), vol. 19, no. 6, pp. 948-955, December, 1984.
[10]Y. Cong and R. L. Geiger, “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays,” IEEE Transactions on Circuits and Systems II (TCAS II), vol. 47, no. 7, pp. 585-595, July. 2000.
[11]Michael J. McNutt, Sabine LeMarquis, and James L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal of Solid-State Circuits (JSSC), vol. 29, no. 5, pp. 611-616, May, 1994
[12]Venkataramana Ajjarapu and Zaid Albanna, “Application of Genetic Based Algorithms to Optimal Capacitor Placement,” Proc. Applications of Neural Networks to Power Systems (ANNPS), pp. 251-255, Jul, 1991.