當閘極通道微縮至奈米(nm)元件時，其所面臨到短通道效應(SCE)影響將越增顯著，然而如何有效將其尺寸微縮之影響考量在外，仍能改善其元件之特性，即為先進半導體製成技術開發之主軸。現今於金氣半場效電晶體元件特性改善又以應變技術最為普及，然而探討於p型通道場效電晶體之改善，又以矽鍺通道層(SiGe- channel) 及接觸蝕刻截止層(CESL)之改變，其元件特性提升最為顯著。實驗中將分別探討施予雙軸應變(SiGe- channel) 及單軸應變 (CESL)之場效電晶體載子遷移速率、驅動電流與低頻雜訊等元件特性，並分析藉由應變技術所製成元件，於閘極介電層缺陷密度(Not)所可能之影響．最後，將改變其操作溫度，深入了解雙軸應變及單軸應變元件於缺陷及溫度之間相關性，即為實驗論文之主旨。

As the gate length of the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is scaled down into the sub-100-nm regime, short-channel effect (SCE) will degrade device performance. The performance enhancement without minimizing the gate length is strongly required. In order to achieve not only downsizing of device dimension but also improving of device performance, semiconductor technologies need to be developed.
Recently, strain-channel engineering is considered a promising tread to improve performance for CMOS devices. Silicon-Germanium (SiGe) channel or highly compressive of contact-etch-stop-layer (CESL) are the popular technologies to improve mobility of p-channel MOSFETs. In experiments, we discuss the impact of biaxial-strain (SiGe-channel) and uniaxial-strain (CESL) on device mobility, drain current, and flicker noise. We also study the oxide-trap densities (Not) in gate-dielectric of p-channel MOSFETs under biaxial- and uniaxial-strain. Finally, we study the impact of temperature on biaxial- and uniaxial-strain in flicker noise and random telegraph signal Nosie (RTN) characteristics.

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