為了高解析度顯示的需求，本論文提出了一個基於非等向性機率神經網路的影像插補方法。非等向性機率神經網路可針對平滑、銳利不同的影區域調整平滑參數並同時考慮影像邊緣方向。一個單神經元的模型被用來估測出適當的平滑參數用於非等向性機率神經網路插補。單神經元的模型參數則透過粒子群最佳化(PSO)方法來求得。實驗的結果顯示出本論文提出的方法在影像邊緣的區域得到好的銳利度表現，在平滑的區域同時具有雜訊抑制的效果。
在嵌入式系統中進行即時的影像插補，本論文提出了一個硬體化的非等向性機率神經網路實現在FPGA上。本文使用VHDL硬體描述語言來實現非等向性機率神經網路，並且採用定點小數進行數值運算。在非等向性機率神經網路影像插補的應用中，硬體化的非等向性機率神經網路被嵌入式處理器視為一個運算加速器。比較軟體與硬體非等向性機率神經網路實現的結果，硬體實現的影像品質與軟體實現結果維持低失真，具備FPGA運算加速器的嵌入式處理器讓運算時間快了158倍。
非等向性機率神經網路的視訊插補器使用管線化架構提高了處理能力。為了對應各種可能的輸入與輸出設定，視訊插補器藉由一個非同步FIFO使輸入與輸出可以使用不同的clock。實現在FPGA上的非等向性機率神經網路的視訊插補器其輸出最高頻率為79.64MHz，輸入最高頻率為76.96MHz。當輸入與輸出頻率在62.21MHz時，視訊插補器在每秒產生30影像的情形下支援最大輸出與輸入的解析度為1920*1080。

For the reason that the demand of high resolution display, this dissertation proposes a novel image interpolation method based on an anisotropic probabilistic neural network (APNN). This APNN interpolation method adjusts the smoothing parameters for varied smooth/edge regions, and considers edge direction. For the optimization of smoothness/sharpness, a single neuron, with particle swarm optimization (PSO) algorithm, is used for the adaptive estimation of APNN’s parameters at each image pixel. The experimental results demonstrate that the proposed method achieves better sharpness enhancement at edge regions, and reveals the noise reduction at smooth region.
Image interpolation requires real-time interpolating to be realized in an embedded system. This study proposes an approach to implement an APNN based on FPGA to interpolate images. The APNN layers were designed with fixed-point arithmetic-employing, synthesizable, VHDL code for FPGA implementation. The FPGA-based APNN was taken as an accelerator of embedded processor, which can be an effective computation module for APNN image interpolation. Both software-based and FPGA-based image interpolation were implemented and evaluated using an APNN. Experimental results showed that the FPGA implementation was approximately 158 times faster than that of the embedded processor with lower loss quality.
Pipeline architecture is used in video scaler to increase the throughput. The lookup table method is used to replace single neuron in estimation of smoothing parameter to improve the speed of operation. To support the many possibilities of input and output configurations, the video scaler with separate clock domains using asynchronous FIFO buffer. For the FPGA, the clock frequency report showed the APNN interpolation output maximum frequency is 79.64MHz. The critical frequency is 76.96MHz for the modules produce the inputs of APNN. While input and output frequency are at 62.21 MHz, the max input and output rectangle size is 1920x1080 to produces video at 30 frames per second (FPS).

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