本論文提出一操作在0.5伏特，具溫度補償機制之非石英式時脈產生器。此架構利用溫度補償電路，針對晶片溫度改變時，將調整時脈產生器之操作頻率，校正到系統所需之操作頻率。當溫度改變時，溫度補償電路利用環形振盪器輸出頻率變化。將其輸出頻率經過時間轉數位轉換器作運算，並送入數位濾波器中，對數位控制振盪器做頻率補償。若校正頻率的幅度不足時，可以調整時間放大器的增益值，將溫度補償電路的修正幅度提高。
本論文之全數位式非石英式時脈產生器使用TSMC 65 nm 1P9M CMOS製程實現晶片，當溫度變化從0°C到100°C時，此全數位非石英式時脈產生晶片之操作頻率可達到300 MHz且操作電壓為0.5 V。其架構實現於65 nm CMOS製程下，電路面積為422×353 um2。其功率消耗為1.05 mW且操作頻率精準度達到±2%。因此，全數位非石英式時脈產生器架構將容易整合於低電壓之操作與數位系統之應用。

A low voltage all digital crystal-less clock generator (CLCG) is presented. All digital CLCG adopts the temperature compensation circuit to calibrate the CLCG operational frequency. The temperature compensation circuit adjusts the operational frequency of CLCG to achieve the target frequency. The temperature compensation adopts ring oscillator to detect the temperature variations. When the temperature varies, the temperature compensation circuit creates the compensation code and feeds the digital code to digital loop filter (DLF). The DLF output codes can adjust the digital control oscillator (DCO) output frequency. If the target frequency is not arrived, The timing amplifier (TA) gain can be adjusted for frequency compensation.
The experimental chip was fabricated by TSMC 65 nm 1P9M CMOS process. Under the temperature is from 0°C to 100°C, the all-digital CLCG output produces a target frequency of 300 MHz under the 0.5 V supply voltage. The core area is 422×353 um2 in a 65 nm CMOS process. The power consumption and frequency accuracy of CLCG are less than 1.05 mW and ±2%, respectively. This all digital CLCG is suitable for low supply voltage applications and digital systems.

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