隨著摩爾定律和Dennard縮放定理的演進，計算機處理器單元的性能得到了改善。然而隨著雲儲存伺服器、人工智慧(AI)和物聯網(IoT)應用程序技術不斷的提升，高性能與低功耗設備的元件在設計記憶體電路上受到廣泛的重視。近來鐵電相關元件被視為能實現低功耗操作和非揮發性記憶體的應用，鐵電記憶體近期在二氧化鉿(HfO2)中發現鐵電特性，此外HfO2與當前CMOS製程技術具相容性與擴展性，有機會適用於各項設備應用因而受到廣大的重視。本篇論文基於夾層HfO2提出非揮發性分離式閘極鐵電場效電晶體記憶體(SG-FeFET NVM)並與傳統單閘極式鐵電場效電晶體記憶體(FeFET)做特性比較，根據物理見解設計提升鐵電記憶體的特性。
本篇論文比較非揮發性記憶體SG-FeFET和FeFET之記憶體視窗 (Memory Window, MW)和讀取電流比(IR1/IR0)。利用TCAD模擬軟件配合鐵電Preisach模型模擬SG-FeFET和FeFET。足夠大的MW對於非揮發性鐵電記憶體的儲存保留與耐久性要求至關重要，因此文中針對SG-FeFET提出新穎序列式寫入藉此提升MW、IR1/IR0與操作能量。我們同時分析閘極長度(LG)在SG-FeFET和FeFET對MW與IR1/IR0的影響，我們的結果顯示與FeFET相比，SG-FeFET配合新穎序列式寫入模式可以在記憶體特性上獲得提升。
此外我們針對SG-FeFET與FeFET在調變不同閘極長度下的能量效率進行分析，結果顯示和FeFET相比在相同閘極長度和電壓條件下SG-FeFET具有較好的MW和相似的寫入能量。然而，SG-FeFET可以透過降低寫入電壓達到和FeFET相同的MW，同時降低寫入能量。本論文也針對鐵電厚度和鐵電參數對記憶體特性的影響進行分析。
最後針對SG-FeFET元件在類神經網路計算上的特性進行分析，結果顯示透過不同脈衝可以調變cell之權重(Weight)，同時展現不錯的調變線性度，SG-FeFET在類神經應用中具有良好的特性。本篇論文提出之SG-FeFET結構有機會實現在深度學習(Deep NeuroNetworks, DNNs)、非揮發性記憶體的設計和低功耗之AI與IoT的運用。

With the advent of Moore’s law and Dennard’s scaling theory, the performance of processor units in computers improved. However, with the successive development of cloud data storage, Artificial Intelligence (AI) and the Internet of Thing (IoT) applications, the need of high performance and low power devices have gained considerable attention for designing memory circuits. Recently, ferroelectric based devices are actively considered for low power Non-Volatile Memory (NVM) applications. The primary reason for the recent activities in ferroelectric based memory is the discovery of ferroelectricity in HfO2. Moreover, due to the scalability and compatibility of HfO2 with present CMOS technology, ferroelectric based memories are considered a promising candidate for various applications. Therefore, the thesis reports on the potential benefits of emerging HfO2 based NVM designed with split-gate (SG) device architecture while comparing its performance with conventional ferroelectric memory. The work reported in the thesis provides the physical insights and design guidelines to improve the performance of HfO2 based NVM.
The thesis compares the key metrics such as Memory Window (MW) and read current ratio (IR1/IR0) for split-gate ferroelectric FET (SG-FeFET) (NVM) with the single gate ferroelectric FET (FeFET) NVM. SG-FeFET and FeFET performance is analyzed using TCAD simulation tool coupled with Preisach model. As the wider MW is essential to meet the retention and endurance requirements of ferroelectric based NVM, the thesis proposes novel sequential write scheme to improve the IR1/IR0, MW, and energy efficiency of SG-FeFET NVM. We also analyzed the impact of gate length (LG) on the MW and IR1/IR0 of SG-FeFET and FeFET devices. Our results show that SG-FeFET with novel sequential write scheme has better memory performance compared to FeFET.
In addition, we analyzed the energy efficiency by computing write energy at various LG in both SG-FeFET and FeFET. The result showcases that SG-FeFET with the same LG and write voltage achieves higher memory window and same writing energy compared to FeFET. However, as compared to FeFET NVM, the write voltage and write energy can be lowered to achieve the same MW in SG-FeFET. The thesis also reports on the impact of ferroelectric thickness and parameters on the memory performances.
Finally, the thesis analyzes the application of SG-FeFET structure for neuromorphic computing. Results highlight that different square wave pulses modulate the cell weights and show better linearity response. The preliminary results showcase that SG-FeFET achieves good performance for neuromorphic applications. The work reported in the thesis provides the opportunities for designing NVM, and hardware-level implementation of deep neural networks (DNNs) for low power AI and IoT applications using SG-FEFET structure.

參考文獻
[1] I.R. Committee, "International Roadmap for Devices and Systems," 2016 Edition. More Moore white paper.
[2] M. Lapedus, "FeFETs are a promising next-gen memory based on well-understood material," 2018, https://semiengineering.com/a-new-memory-contender/.
[3] J. Valasek, "Piezo-Electric and Allied Phenomena in Rochelle Salt," Physical Review, vol. 17, pp. 475, 1921.
[4] X. Pan et al., "Retention mechanism study of the ferroelectric field effect transistor, "in Applied Physics Letters, vol. 99, p. 013505, June 2011.
[5] N. Gong et al., "Why Is FE-HfO2 More Suitable Than PZT or SBT for Scaled Nonvolatile 1-T Memory Cell? A Retention Perspective, " in IEEE Electron Device Letters, vol. 37, no. 9, Sept. 2016
[6] T. P. Ma et al., "Why is nonvolatile ferroelectric memory field-effect transistor still elusive?," in IEEE Electron Device Letters, vol. 23, no. 7, pp. 386-388, July 2002, doi: 10.1109/LED.2002.1015207.
[7] T. S. Böscke et al., "Ferroelectricity in hafnium oxide thin films," in Applied Physics Letters, vol. 99, no. 10, p. 102903, May 2011.
[8] M. H. Park et al., "A comprehensive study on the structural evolution of HfO2 thin films doped with various dopants, " J. Mater. Chem. C, vol. 5, no. 19, pp. 4677–4690, 2017
[9] J. Müller et al., "Ferroelectric Hafnium Oxide Based Materials and Devices Assessment of Current Status and Future Prospects," in ECS Journal of Solid State Science and Technology, vol. 4, no.5, February 2015.
[10] J. Müller et al., "Ferroelectric hafnium oxide: A CMOS-compatible and highly scalable approach to future ferroelectric memories," 2013 IEEE International Electron Devices Meeting, Washington, DC, 2013, pp. 10.8.1-10.8.4, doi: 10.1109/IEDM.2013.6724605.
[11] S. Slesazeck et al., "Embedding hafnium oxide based FeFETs in the memory landscape," 2018 International Conference on IC Design & Technology (ICICDT), Otranto, 2018, pp. 121-124, doi: 10.1109/ICICDT.2018.8399771.
[12] S. George et al., "Nonvolatile memory design based on ferroelectric FETs," 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2016, pp. 1-6, doi: 10.1145/2897937.2898050.
[13] M. Abuwasib et al., "CMOS compatible integrated ferroelectric tunnel junctions (FTJ)," 2015 73rd Annual Device Research Conference (DRC), Columbus, OH, 2015, pp. 45-46, doi: 10.1109/DRC.2015.7175545.
[14] F. Mo et al., "Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method," 2019 19th Non-Volatile Memory Technology Symposium (NVMTS), Durham, NC, USA, 2019, pp. 1-5, doi: 10.1109/NVMTS47818.2019.8986219.
[15] J. Hung et al., "Challenges and Trends inDeveloping Nonvolatile Memory-Enabled Computing Chips for Intelligent Edge Devices," in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1444-1453, April 2020, doi: 10.1109/TED.2020.2976115.
[16] S. Dünkel et al., "A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 19.7.1-19.7.4, doi: 10.1109/IEDM.2017.8268425.
[17] K. Ni et al., "Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance," in IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2461-2469, June 2018, doi: 10.1109/TED.2018.2829122.
[18] Hang-Ting Lue et al., "Device modeling of ferroelectric memory field-effect transistor for the application of ferroelectric random access memory," in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 50, no. 1, pp. 5-14, Jan. 2003, doi: 10.1109/TUFFC.2003.1176521.
[19] V. P. Hu et al., "Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications," 2019 Symposium on VLSI Technology, Kyoto, Japan, 2019, pp. T134-T135, doi: 10.23919/VLSIT.2019.8776555.
[20] S. Salahuddin et al., "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. I, No. 2, pp.405-410, 2008.
[21] C. Hu et al., "0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF," 2015 73rd Annual Device Research Conference (DRC), Columbus, OH, 2015, pp. 39-40, doi: 10.1109/DRC.2015.7175542.
[22] V. P. Hu et al., "Negative capacitance enables FinFET and FDSOI scaling to 2 nm node," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 23.1.1-23.1.4, doi: 10.1109/IEDM.2017.8268443.
[23] K. Ni et al., "A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 131-132, doi: 10.1109/VLSIT.2018.8510622.
[24] M. A. Alam et al., "A critical review of recent progress on negative capacitance field-effect transistors," in Applied Physics Letters, vol. 114, p. 090401, Feb. 2019.
[25] Sentaurus TCAD, O-2018-6 Manual
[26] J. Chow et al., "A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits," 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), Honolulu, HI, USA, 2004, pp. 448-449, doi: 10.1109/VLSIC.2004.1346646.
[27] M. Jerry et al., "Ferroelectric FET analog synapse for acceleration of deep neural network training," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 6.2.1-6.2.4, doi: 10.1109/IEDM.2017.8268338.
[28] K. Ni et al., "A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 131-132, doi: 10.1109/VLSIT.2018.8510622.
[29] K. Ni et al., "SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 13.2.1-13.2.4, doi: 10.1109/IEDM.2018.8614496.
[30] T. Ali et al., "A Multilevel FeFET Memory Device based on Laminated HSO and HZO Ferroelectric Layers for High-Density Storage," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 28.7.1-28.7.4, doi: 10.1109/IEDM19573.2019.8993642.
[31] H. J. Kim et al., "Grain size engineering for ferroelectric Hf0.5Zr0.5O2 films by an insertion of Al2O3 interlayer" in Applied Physics Letters., vol. 105, pp.192903, Nov 2014.
[32] S. Riedel et al., "A thermally robust and thickness independent ferroelectric phase in laminated hafnium zirconium oxide," in AIP Advances., vol. 6, pp. 095123, Sept 2016.
[33] I. Yoon et al., "A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations," 2018 76th Device Research Conference (DRC), Santa Barbara, CA, 2018, pp. 1-2, doi: 10.1109/DRC.2018.8442235.
[34] H. Mulaosmanovic et al., "Novel ferroelectric FET based synapse for neuromorphic systems," 2017 Symposium on VLSI Technology, Kyoto, 2017, pp. T176-T177, doi: 10.23919/VLSIT.2017.7998165.
[35] Y. LenCun et al., "Deep learning," Nature, vol. 521, no. 7553, pp. 436-444, May 2015.
[36] L. Deng et al., "Recent advances in deep learning for speech research at Microsoft," in Proc. ICASSP, 2013, pp. 8604-8608.
[37] A. Krizhevsky et al., "ImageNet classification with deep convolutional neural networks," in PROC. NIPS, 2012, PP. 1097-1105.
[38] User Manual of MLP simulator (+NeuroSim) V1.0
[39] P. Chen et al., "NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 6.1.1-6.1.4, doi: 10.1109/IEDM.2017.8268337.
[40] P. Sangho et al., "Neuromorphic speech systems using advanced ReRAM-based synapse," in IEDM Tech Dig. 2013. 25.6.1-25.6.4. 10.1109/IEDM.2013.6724692.
[41] M. Jerry et al., "A ferroelectric field effect transistor based synaptic weight cell," in Journal of Physics D: Applied Physics, vol. 51, pp. 434001, 2018.