| 研究生: |
徐賢名 Hsien-Ming Hsu |
|---|---|
| 論文名稱: |
氧化鉿/氧化鋁/銻化鎵金氧半結構製備與界面缺陷之研究 Interfacial Electrical Properties of HfO2/Al2O3/GaSb MOS Capacitors Prepared by Atomic Layer Deposition |
| 指導教授: |
綦振瀛
Jen-Inn Chyi |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 83 |
| 中文關鍵詞: | 銻化鎵 、金氧半結構 、氧化鉿 、氧化鋁 |
| 相關次數: | 點閱:5 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著科技進步,對於元件效能需求的提高,互補式金氧半場效電晶體的尺寸逐漸微縮,矽材料與閘極氧化層將面臨其物理極限,以三五族材料搭配高介電常數氧化層來取代目前現有矽基電晶體是目前眾人研發的趨勢之一。但是對三五族材料來說,氧化層與半導體界面缺陷的問題仍是目前最需要深入研究的一項課題。本論文即針對此課題,提出兩個有效降低高介電材料/銻化鎵界面缺陷之方法,並分析其金氧半結構之電氣特性。
本論文中首先聚焦於開發臨場沉積的氧化鉿/氧化鋁(5 nm/1 nm)雙層膜於銻化鎵上,希望藉由磊晶後直接於高真空腔體中傳輸的方式,防止表面原生氧化層生成,以降低界面缺陷。研究結果顯示,以此方式製作的金氧半電容,室溫下電容調變率約為31%,界面能態密度約為5.27×1012 eV-1cm-2。
本論文亦提出利用氫氣電漿清理銻化鎵表面的方法,以氫原子與表面原生氧化物進行化學反應,進而去除原生氧化層。實驗結果顯示,在適當的條件下,此方法同樣能達到降低界面缺陷的效果,室溫下電容調變率約為36 %,界面能態密度約為3.81×1012 eV-1cm-2。利用此兩種氧-半界面處理方式有助於元件閘極通道之調控能力,改善次臨界擺幅等電氣特性,使三五族金氧半場效電晶體之實用化再進一步。
According to Moor’s law, the density of transistors on a single integrated circuit chip doubles every 18 months. However, the gain in cost and performance is not commensurate with simple dimension scaling anymore because Si-based transistors are approaching their physical limit, especially in the sub-10 nm regime. This has prompted great interest in high mobility III-V compounds as alternatives of transistor channel materials. However, the native oxides of III-V compounds are complex in structure and composition. They form defects at the oxide-semiconductor interface and hinder the construction of ideal metal-oxide-semiconductor field-effect transistors. In this study, two methods are successfully used to suppress the defect state density of high-κ/GaSb interface as demonstrated in the metal-oxide-semiconductor capacitors (MOSCAPs).
The HfO2/Al2O3 bi-layer oxide films used in this study are deposited on GaSb samples in an atomic layer deposition system that is connected to a molecular beam epitaxy system with ultra-high vacuum transfer chambers. With this tool, the as-grown GaSb can be transferred to the atomic layer deposition system for high-κ deposition with no or little surface native oxides. The MOSCAPs prepared by this method show effective capacitance modulation of 31 % with interface state density of 5.27×1012 eV-1cm-2 at 300 K.
Hydrogen plasma treatment is another method proposed to clean the surface of GaSb before high-κ dielectric deposition. The native oxide on GaSb, which has been exposed to air, is effectively removed through the chemical reactions with hydrogen radicals. The MOSCAPs prepared by this method show effective capacitance modulation of 36 % with interface state density of 3.81×1012 eV-1cm-2. The result obtained in this work is encouraging toward the realization of GaSb MOSFETs with high on/off ratio and low sub-threshold swing.
[1] C. A. K. Mistry, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau*, C.-H. Choi,, K. F. G. Ding, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He#, J. Hicks , R. Huessner, D. Ingerly,, R. J. P. Jain, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz#, B. McIntyre, P. Moon, J. Neirynck, S. Pae,, D. P. C. Parker, C. Prasad#, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren°, J. Sebastian, J. Seiple,, and S. S. D. Simon, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki, "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEEE International Electron Devices Meeting, pp. 247 - 250, 2007.
[2] M. Bohr, "The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era," IEEE International Electron Devices Meeting, pp. 1.1.1 - 1.1.6, 2011.
[3] T.S. T. I. C. Tsai, C.J. Su, H.C. Lin, T.Y. Huang, Y.J. Wei , "Low Temperature Polycrystalline Si Nanowire Devices with Gate-All-Around Al2O3/TiN Structure Using An Implant-Free Technique," IEEE Nanoelectronics Conference, pp. 1 - 2, 2011.
[4] H. R. L. Bijesh, H. Madan, D. Mohata, W. Li, N.V. Nguyen, D. Gundlach, C.A. Richter, J. Maier, K. Wang, T. Clarke, J.M. Fastenau, D. Loubychev, W.K. Liu, V. Narayanan, S. Datta, "Demonstration of In0.9Ga0.1As/GaAs0.18Sb0.82 Near Broken-gap Tunnel FET with ION=740 μA/μm, GM=700 μS/μm and Gigahertz Switching Performance at VDS=0.5 V," IEEE International Electron Devices Meeting, pp. 28.2.1 - 28.2.4, 2013.
[5] A. J. Strojwas, "Is the bulk vs. SOI battle over?," VLSI Technology, pp. 1 - 2, 2013.
[6] J. A. del Alamo, "Nanometre-scale electronics with III-V compound semiconductors," Nature, vol. 479, pp. 317-23, Nov 17 2011.
[7] Hai-Dang Trinh, Yue-Chin Lin, Edward Yi Chang, Senior member, Hong-Quan Nguyen, Shin-Yuan Wang, Yuen-Yee Wong, Binh-Tinh Tran, Quang-Ho Luc, Chi-Lang Nguyen, and Chang-Fu Dee, "Influence of post deposition annealing temperatures," ICSE, 2012.
[8] K. Mo¨ller, L. To¨ben, Z. Kollonitsch, Ch. Giesen, M. Heuken, F. Willig, T. Hannappel, "In-situ monitoring and analysis of GaSb(100) substrate deoxidation," Applied Surface Science, vol. 242, pp. 392-398, 2005.
[9] A. Ali,H. S. Madan, A. P. Kirk, D. A. Zhao, D. A. Mourey, M. K. Hudait, R. M. Wallace, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta, "Fermi level unpinning of GaSb (100) using plasma enhanced atomic layer deposition of Al2O3," Applied Physics Letters, vol. 97, p. 143502, 2010.
[10] Aneesh Nainani, Toshifumi Irisawa, Ze Yuan, Brian R. Bennett, J. Brad Boos, "Optimization of the Al2O3/GaSb Interface and a High-Mobility GaSb pMOSFET," IEEE Transactions on Electron Devices, vol. 58, 2011.
[11] Z. Z. Tan, L. Wang, J. Xu, "Improved Properties of HfO2/Al2O3/GaSb MOS Capacitors Passivated with Neutralized (NH4)2S Solutions," ECS Solid State Letters, vol. 2, pp. P61-P62, 2013.
[12] E. R. Cleveland, L. B. Ruppalt, B. R. Bennett, and S. M. Prokes, "Effect of an in situ hydrogen plasma pre-treatment on the reduction of GaSb native oxides prior to atomic layer deposition," Applied Surface Science, vol. 277, pp. 167-175, 2013.
[13] L. B. Ruppalt, E. R. Cleveland, J. G. Champlain, S. M. Prokes, J. Brad Boos, D. Park, et al., "Atomic layer deposition of Al2O3 on GaSb using in situ hydrogen plasma exposure," Applied Physics Letters, vol. 101, p. 231601, 2012.
[14] T. Suntola, "Atomic Layer Epitaxy," ASR, vol. 4, pp. 261-312, 1989.
[15] L. C. d. B. t. t. C. b. L. C. d. Carvalho, "X-ray photoelectron spectroscopy," 2009.
[16] D. K.SCHRODER, "Semiconductor Material and Device Characterization," 2006.
[17] E. H. Nicollian and A. Goetzberger: “, "The Si-SiO2 Interface - Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique," Bell Syst. Tech. J, vol. 46, pp. 1055-1133, 1967.
[18] 許哲瑋, "氧化鉿∕砷化銦金氧半結構之製備及其介面與電性研究," 國立中央大學, 2012.
[19] R. Engel-Herbert, Y. Hwang, and S. Stemmer, "Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces," Journal of Applied Physics, vol. 108, p. 124101, 2010.
[20] P. M. T. L. J. Whitman, † S. C. Erwin, B. R. Bennett, and B. V. Shanabrook, "Metallic III-V (001) Surfaces: Violations of the Electron Counting Model," Physical Review Letters, vol. 79, 1997.
[21] R. L. V. Puurunen, Wilfried Besling, Wim F. A. Richard, Olivier Bender, Hugo Conard, Thierry Zhao, Chao Delabie, Annelies Caymax, Matty De Gendt, Stefan Heyns, Marc Viitanen, Minna M. de Ridder, Marco Brongersma, Hidde H. Tamminga, Yde Dao, Thuy de Win, Toon Verheijen, Marcel Kaiser, Monja Tuominen, Marko, "Island growth in the atomic layer deposition of zirconium oxide and aluminum oxide on hydrogen-terminated silicon: Growth mode modeling and transmission electron microscopy," Journal of Applied Physics, vol. 96, p. 4878, 2004.
[22] T. Yang, "Capacitance-Voltage studies of Atomic-Layer-Deposited MOS structure on Gallium Arsenide And other Ⅲ-Ⅴ Compound Semiconductor," Purdue University, 2007.
[23] E. J. W. Kim, Lingquan Asbeck, Peter M. Saraswat, Krishna C. McIntyre, Paul C., "Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals," Applied Physics Letters, vol. 96, p. 012906, 2010.
[24] A. Molle, L. Lamagna, C. Grazianetti, G. Brammertz, C. Merckling, M. Caymax, et al., "Reconstruction dependent reactivity of As-decapped In0.53Ga0.47As(001) surfaces and its influence on the electrical quality of the interface with Al2O3 grown by atomic layer deposition," Applied Physics Letters, vol. 99, p. 193505, 2011.
[25] Yu Yuan, Lingquan Wang, Bo Yu, Byungha Shin, Jaesoo Ahn, Paul C. McIntyre, Peter M. Asbeck, Mark J. W. Rodwell, and Yuan Taur, "A Distributed Model for Border Traps in Al2O3 − InGaAs MOS Devices," IEEE Electron Device Letters, vol. 32, 2011.
[26] S. Stemmer, V. Chobpattana, and S. Rajan, "Frequency dispersion in III-V metal-oxide-semiconductor capacitors," Applied Physics Letters, vol. 100, p. 233510, 2012.
[27] Yueh-Chin Lin, Mao-Lin Huang, Chen-Yu Chen, Meng-Ku Chen, Hung-Ta Lin, Pang-Yan Tsai, Chun-Hsiung Lin, Hui-Cheng Chang, Tze-Liang Lee, Chia-Chiung Lo, Syun-Ming Jang, Carlos H. Diaz, He-Yong Hwang, Yuan-Chen Sun, and Edward Yi Chang, "Low interface trap density Al2O3/In0.53Ga0.47As MOS capacitor fabricated on MOCVD-grown InGaAs epitaxial layer on Si substrate," Applied Physics Express, vol. 7, p. 041202, 2014.
[28] Wipakorn Jevasuwan*, Tatsuro Maeda, Noriyuki Miyata, Minoru Oda, Toshifumi Irisawa, Tsutomu Tezuka, and Tetsuji Yasuda, "Self-limiting growth of ultrathin Ga2O3for the passivation of Al2O3/InGaAs interfaces," Applied Physics Express, vol. 7, p. 011201, 2014.