複晶矽薄膜電晶體相較於非晶矽薄膜電晶體具有較高的載子遷移率與驅動電流，因此廣泛應用於各種領域上，包含主動式液晶顯示器及三維積體電路，而這項技術被喻為最有希望實現將積體電路建立在玻璃面板(system on panel, SOP)作為控制端與記憶元件。然而元件在汲極端的高電場導致許多不理想效應的發生，例如: 漏電流效應、熱載子效應、扭結效應等。為了改善這些不理想效應，過去的學者提出許多不同的結構去改善元件汲極端的高電場，例如:Offset、Lightly Doped Drain (LDD)、Raised Source/Drain(RSD)以及Field-Induced Drain(FID)等結構。雖然這些結構能有效抑制不理想效應的發生，但也同時增加寄生電阻導致元件開電流下降，或者需要額外的光罩及離子佈值增加製程的複雜度。因此提出一個只需幾種簡單的製程，無需昂貴製程步驟的新式結構成為我們研究的動機。
在本文中我們提出一個“新式薄膜電晶體結合閘極內保護汲極電極之設計”，此結構利用在閘極層下方新增一個獨立的汲極電極層，藉由與通道的汲極電極相接在一起形成等電位，可以使的通道與汲極端的接面處電壓差趨近於零，分散通道與汲極端接面處的電場。經由我們使用ISE-TCAD模擬結果顯示，汲極端的高電場與離子化碰撞都有大幅的改善，因此有效降低漏電流，使元件有良好的開關電流比。而在製程方面也不需額外昂貴的製程，故當此元件應用於大面積的顯示器上，對於提升元件與電路效益有極大的幫助。

Polycrystalline silicon thin film transistors have been attracted for using in various fields, including active matrix liquid crystal displays (AMLCDs) and 3-D integrated circuits because of their high carrier mobility and driving current. The technology is the promised candidate for the ultimate goal of building fully integrated flat panel display system-on-panel (SOP) as a controller and memory. However, a high electric field (EF) near the channel/drain region causes several undesirable effects, such as large leakage current, kink effect and hot carrier effect in TFT. In order to overcome those drawbacks, previous studies used a lot of structures such as offset, Lightly Doped Drain (LDD)、Raised Source/Drain(RSD) and Field-Induced Drain(FID) to reduce the high electric field in the device. Although many of these structures can effectively reduce the electric field, increase the parasitic resistance is lowered a lot of on-current, or require additional mask ion implantation and increased process complexity and cost. Therefore, we propose a structure which requires only a few simple processes, without requiring expensive processing steps to improve the practical value of this device.
In this paper, we propose a structure entitled “A Novel Thin Film Transistor With Gate Sheltered Drain Design”. Its feature owing to add a additional drain electrode underneath the gate layer, and the sheltered drain is connected to the drain electric potential can distribute the electric field near the channel/drain region because of the potential difference is close to zero. According to our simulation results, the high electric field (EF) and impact ionization (IMP) are substantial improved near the channel/drain region and effectively reduce the leakage current which will make the device have a good ON/OFF current ratio. The new structure also without requiring expensive processing steps and it will be beneficial to circuit efficiency when the devices are applying to large area microelectronics by using our new concept devices.

參考文獻
[1] 友達光電股份有限公司著作: 技術研發>TFT-LCD 簡介>LTPS, 網址:
http://auo.com/auoDEV/technology.php?sec=LTPS&ls=tc
[2] S. D. Brotherton, “Topical review Polystalline silicon thin film transistors” Semicond. Sci. Technol., 10, p721-738, 1995.
[3] G. Radnoczi, A. Robertsson, H. T. G. Hentzell, S. F. Gong, and M.‐A. Hasan, “Al induced crystallization of a-Si,” J. Appi. Phys., vol. 69, No. 9, pp. 6394-6399, May 1991.
[4] S. F. Gong, H. T. G. Hentzell, A. E. Robertsson, L. Hultman, S.‐E. Hörnström, and G. Radnoczi, “Al-doped and Sb-doped polycrystalline silicon obtained by means of metal-induced crystallization” J. Appi. Phys., vol. 62, No. 9, pp. 3726-3732 Nov. 1987.
[5] T. J. Konno, R. Sinclair, “Metal contact induced crystallization of semiconductors,” Materials Science Engineering, vol. A179-180, part1, pp426-432, 1994.
[6] L. Hultman, A. Robertsson, H. T. G. Hentzell, I. Engström, and P. A. Psaras, “Crystallization of Amorphous Silicon During Thin-Film Gold Reaction” J. Appi. Phys. 62, pp. 3647-3655, Nov. 1, 1987.
[7] N. Kubo, N. Kusummoto, T. Inushima, and S. Yamazaki, “Characterization of polycrystalline-Si thin film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, 40, 1876, 1994
[8] G. K. Giust and T. W. Sigmon, “High-performance thin-film transistors fabricated using excimer laser processing and grain engineering”, IEEE Trans. Electron Devices, 43, 561, 1996
[9] M. Cao, S. Talwar, K. J. Kramer, T. W. Sigmon, and K. C. Saraswat, “A high-performance polysilicon thin-film transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films”, IEEE Trans. Electron Devices, 43, 561, 1996
[10] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction Mechanism of Leakage Current Observed in Metal-Oxide-Semiconductor Transistors and Poly-Si Thin Film Transistors,” Jpn. J. Appl. Phys., Vol. 31, no. 2, pp. 206-209, Feb. 1992.
[11] J. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, “Anomalous Leakage Current in LPCVD Polysilicon MOSFET’s,” IEEE Trans. Electron Devices, vol. 32, no. 9, pp. 1878-1884, Sep. 1985.
[12] K. R. Olasupo and M. K. Hatalis "Leakage current mechanism in submicron polysilicon thin-film transistors", IEEE Trans. Electron Devices, vol. 43, no. 8, pp.1218 -1223, 1996
[13] M. Lack, I.-W. Wu, T. J. King, A. G. Lewis, ”Analysis of leakage currents in poly silicon thin film transistors,”in IEDM Tech. Dig., 1993, pp.385-388.
[14] E.Takeda "Hot-carrier effects in submicrometer MOS VLSIs", Proc. Inst. Elect. Eng. I—Solid-State Electron Devices, vol. 131, no. 5, pp.153 -162 1984
[15] E. Takeda , N. Suzuki and T. Hagiwara "Device performance degradation to hot-carrier injection at energies below the Si-SiO2 energy barrier", Proc. IEEE Int. Electron Dev. Meeting, vol. 29, pp.396 -399 1983
[16] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, and I. Policicchio, “ Floating body effects in polysilicon thin-film transistors” , IEEE TED, vol. 44,pp.2234–2241,1997
[17] A. Valletta, P. Gaucci, L. Mariucci, G. Fortunato, “Modellling velocity saturation and kink effects in p-channel polysilicon thin film transistors,” thin solid films, vol.515, pp. 7417-7421, 2005.
[18] L. Mariucci, G. Fortunato, A. Bonfiglietti, M. Cuscuna, A. Pecora, and A. Valletta, “ Polysilicon TFT structures for kink-effect suppression,” IEEE TED, vol. 51, pp. 1135–1142, 2004
[19] D. D. Venuto, M. J. Ohletz, ”Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits,”Microelectronics Journal, vol. 34, pp889-895, 2003.
[20] S.Bindra, S. Haldar , R.S.Gupta, ”Modeling of kink effect in polysilicon thin film transistor using charge sheet approach,”Solid State Electronics, vol 47, pp.6445-651, 2003.
[21] A. Kumar K. P., J. K. O. Sin, C. T. Nguyen, and P. K. Ko, “Kink-Free Polycrystalline Silicon Double-Gate Elevated Channel Thin-Film Transistors,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2514-2520, Dec. 1998.
[22] P. Y. Kuo, T. S. Chao, and T. F. Le, “Suppression of the Floating-Body Effect in poly Si thin film transistors with self aligned schottky barrier source and ohmic body contact structure,”IEEE Electron Device Lett., vol. 25, no9, 2004.
[23] J.I. Han, G.Y. Yang, and C.H. Han, “A New Self-Aligned Offset Staggered Polysilicon Thin-Film Transistor,”IEEE Electron Device Lett., VOL. 20, NO. 8, 1999.
[24] P. S. Shih, C. Y. Chang, T. C. Chang, T. Y. Huang, D. Z. Peng, and C. F. Yeh, “A Novel Lightly Doped Drain Polysilicon Thin-Film Transistor with Oxide Sidewall Spacer Formed by One-Step Selective Liquid Phase Deposition,” IEEE Electron Device Lett., vol. 20, pp. 421–423,1999
[25] F.T. Chien, C.W. Chen, C.N. Liao, T.C. Lee, C.L. Wang, C.H. Cheng, H.C. Chiu, and Y.T. Tsai, “A Novel Self-Aligned Raised Source/Drain Polysilicon Thin-Film Transistor With a High-Current Structure,“ IEEE Electron Devices Lett., vol. 32, No. 8, Aug. 2011
[26] K. Ohgata, Y. Mishima, and N. Sasaki, “A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” in IEDM Tech. Dig., San Francisco, CA, 2000, pp. 205–208.
[27] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato,” Characteristics of Field-Induced-Drain (FID) Poly-Si TFT's with High ON/OFF Current Ratio,” IEEE Trans. Electron Devices, vol.39, no. 4, pp. 916-920, Apr. 1992.
[28] A. J. Walker , S. Nallamothu , E. H. Chen , M. Mahajani , S. B. Herner , M. Clark , J. M. Cleeves , S. V. Dunton , V. L. Eckert , J. Gu , S. Hu , J. Knall , M. Konevecki , C. Petti , S. Radigan , U. Raghuram , J. Vienna and M. A. Vyvoda "3D TFT-SONOS memory cell for ultra-high density file storage applications", VLSI Symp. Tech. Dig., pp.29 -30 2003
[29] A. G. Lewis, I.-W. Wu, T. Y. Huang, A. Chiang, and R. H. Bruce, “Active matrix liquid crystal display design using low and high temperature processed polysilicon TFTs,” in IEDM Tech. Dig., San Francisco, CA, 1990, pp. 843–846.
[30] T. Shimoda, H. Ohshima, S. Miyashita, M. Kimura, T. Ozawa, I. Yudasaka, H. Kobayashi, R. H. Friend, J. H. Burroughes, and C. R. Towns, “High resolution light emitting polymer display driven by low temperature polysilicon thin film transistor with integrated driver,” in Proc. ASID, Seoul, Korea, 1998, pp. 217–220.
[31] X. Duan, Y. Huang, and C. M. Lieber, “Nonvolatile memory and programmable logic from molecule-gated nanowires,” Nano Lett., vol. 2, no. 5, pp. 487–490, 2002.
[32] T. Y. Huang, I. W. Wu, A. G. Lewis, A. Chiang, and R. H. Bruce, “A simpler 100-V polysilicon TFT with improved turn-on characteristics,” IEEE Electron Device Lett., vol. 11, no. 6, pp. 244–246, Jun. 1990.
[33] K. Tanaka, K. Nakazawa, S. Suyama, and K. Kato, “Characteristics of field-induced-drain (FID) poly-Si TFT’s with high on/off current ratio,” IEEE Trans. Electron. Devices, vol. 39, pp. 916–920, 1992.
[34] M.C. Lee and M.K. Han, “Poly-Si TFTs With Asymmetric Dual-Gate for Kink Current Reduction,” IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 1, JANUARY 2004
[35] ISE-TCAD Manuals, release 10.0, Integr. Syst. Eng. AG, Zurich, Switzerland, 2004
[36] 陳志強編著 “LTPS低溫複晶矽顯示器技術” 全華科技圖書股份有限公司p.2-05~2-07 2004
[37] N.I. Lee , J.W. Lee , H.S. Kim and C.H. Han , “High-Performance EEPROM’s Using N- and P-Channel Polysilicon Thin-Film Transistors with Electron Cyclotron Resonance N O-Plasma Oxide,” IEEE Electron Device Lett., vol. 20, no. 1, pp.15 -17, 1999
[38] J.H. Oh , H.J. Chung , N.I. Lee and C.H. Han "A high-endurence low-temperature polysilicon thin-film transistor EEPROM cell", IEEE Electron Device Lett., vol. 21, no. 6, pp.304-306, 2000
[39] S. Zhang, C. Zhu, J. K. O. Sin, and P. K. T. Mok, “A Novel Ultrathin Elevated Channel Low-Temperature Poly-Si TFT,” IEEE Electron Device Lett., vol. 20, no. 11, pp. 569-571, Nov. 1999.
[40] S. Zhang, C. Zhu, J. K. O. Sin, J. N. Li, and P. K. T. Mok, ” Ultra-Thin Elevated Channel Poly-Si TFT Technology for Fully-Integrated AMLCD System on Glass,” IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 569-575, Mar. 2000.
[41] H. H. Berger，Solid-State Electron， vol. 15，pp. 145，1972.