本論文主要為設計研製收發機前端之低雜訊放大器及功率放大器，包含兩個分別操作於C/Ku頻帶的低雜訊放大器及兩個操作於Ka頻帶的功率放大器。第二章首先使用台積電 0.18 μm CMOS製程設計三級疊接低雜訊放大器，小訊號增益達到22.4 dB，3 dB頻寬從11至19 GHz，頻率在15 GHz時有最小雜訊指數4 dB，晶片面積為0.84 x 0.8 mm2。進一步將疊接架構修改為共源極，以減少低雜訊放大器之直流功率消耗。電路使用穩懋 0.15 μm GaAs製程實現，包括三級共源極增益級，小訊號增益達到28 dB，3 dB頻寬從4至16 GHz，頻率在10 GHz時有最小雜訊指數2 dB，晶片面積為2 x 1 mm2。
第三章使用穩懋 0.1 μm GaAs製程設計一個Ka頻帶雙功率合併功率放大器，使用雙合併技術來提升輸出功率，第一級增益單元串聯一組電阻-電容並聯來改善穩定度，第二級則兩兩電晶體合併，共合併四顆電晶體。另介紹放大器穩定度檢查電路，除了檢查放大器整體電路的穩定係數K值，檢查多級放大器穩定度時作級間穩定度模擬，以及檢查大功率電路穩定度的非線性穩定度模擬，以及加入奇模抑制電阻後進行的奇模穩定度模擬。其量測得小訊號增10 dB，3 dB頻寬為從33至43 GHz，輸入1 dB增益壓縮點(IP1dB)約為16 dBm，而輸出1 dB增益壓縮點(OP1dB)約為24.6 dBm，飽和功率(Psat) 為26 dBm，功率消耗為2084 mW，晶片面積為2 x 1 mm2。
在第四章使用台積電 90 nm CMOS製程設計層疊式功率放大器。同樣使用雙合併技術來作功率整合，而為了在取得足夠輸出功率時，也能有足夠的增益頻寬表現，使用T型匹配於功率放大器的匹配網路。第一級增益單元使用層疊式以增加電路增益，第二級則兩兩並聯層疊式合併作為功率元以取得較高的輸出功率。其量測得小訊號增益10.3 dB，3 dB頻寬為從30至48 GHz，輸入1 dB增益壓縮點(IP1dB)約為5 dBm，而輸出1 dB增益壓縮點(OP1dB)約為14 dBm，飽和功率(Psat) 為16 dBm，功率消耗為765 mW。且可藉由提升汲極偏壓到2.8V，於30至39 GHz頻率範圍得到大於16 dBm的飽和功率，且於31 GHz得到最高19 dBm的飽和功率，晶片面積為 0.88 x 0.84 mm2。
最後，於第五章呈現被動式二極體混波器以及接收器前端電路的設計。本設計是使用穩懋增強-空乏模態( ED Mode ) 0.15 μm GaAs製程。二極體混波器的有效操作頻帶範圍是從25 GHz到50 GHz，並且訂定38 GHz為電路中心頻率。在10 dBm的本地振盪驅動源的情況下，表現出的轉換增益約為-6 dB，晶片面積為1 x 1 mm2。而二極體混波器受益於本身被動的設計，直流功耗甚小。後整合穩懋0.15 μm GaAs製程的Ka頻帶低雜訊放大器，最後實現一個Ka頻帶接收器前端電路，擁有27-37 GHz的RF操作頻率，轉換增益最高為31 dB，雜訊指數2 dB，輸入1 dB增益壓縮點為-6 dBm，晶片面積為3 x 1.5 mm2。

In this thesis, design of several C/Ku bands low noise amplifiers (LNAs) and power amplifiers (PAs) are presentd. A Ku-band three-stage cascode LNA using TSMC 0.18 μm CMOS process is presented in Chapter 2. The cascode CMOS LNA exhibits a 22.4-dB gain, 3-dB bandwidth from 11 to 19 GHz, a minimum noise figure of 4 dB at 15 GHz. The chip size of the three-stage LNA is 0.84 x 0.8 mm2. A broadband LNA is designed using common-source (CS) topology to reduce dc power consumption, and the circuit is fabricated in 0.15 μm GaAs process provided by WIN Semiconductors Corporation. The three-stage GaAs LNA exhibits a 28-dB gain, 3-dB bandwidth from 4 to 16 GHz, a minimum noise figure of 2 dB at 10 GHz. The chip size of the three-stage LNA is 2 x 1 mm2.
In Chapter 3, a Ka-band binary-combined power amplifier using WIN 0.1 μm GaAs procss is presented. The first stage uses a resistor-capacitor network to improve stability. The second stage combines 4 FETs with a total gate periphery of 800 μm. The stability analysis is summarized, including K factor, interstage stability, non-linear stability, and odd mode stability after adding the odd-mode suppression resistors . The PA exhibits a 10-dB gain, 3 dB bandwidth from 30 to 43 GHz , an output 1-dB compression point of 24.6 dBm, and a saturation output power of 26-dBm. The chip size of the PA is 2 x 1 mm2.
A CMOS stacked PA is presented in Chapter 4. The first stage uses a stacked structure as the gain unit to increase the gain performance, and the second stage combines two power units of stacked structure in parallel to achieve higher output power. In order to further improve the broadband gain frequency response with high output power, the T-model matching network is employed in the matching network of the PA. The stacked PA exhibits 10.3-dB gain, 3-dB bandwidth from 30 to 48 GHz, an output 1-dB compression point of 14 dBm, and a saturation output power of 16-dBm. The DC power comsumption is 765 mW. The chip size of the PA is 0.88 x 0.84 mm2.
Finally, design of the Ka-band GaAs diode mixer is presentd, the mixer has 3 dB bandwidth between 25 GHz and 50 GHz with a center frequency of 38 GHz. The diode mixer shows up to a conversion gain of -6-dB with a 10-dBm local oscillation (LO) driving power, without DC power consumption. The chip size of the mixer is 1 x 1 mm2. The mixer is further integrated with a 4-stage LNA to lower noise figure for some Ka-band receiving applications. The integrated front-end circuit shows a 31-dB conversion gain with a 10 dBm LO driving power, 2-dB noise figure and an output 1 dB gain compression point is -6 dBm. The chip size of the front- end circuit is 3 x 1.5 mm2.

[1] Y.Shim, C.-W. Kim, J. Lee, and S.-G. Lee, “Design of Full Band UWB Common-Gate LNA”, IEEE Microw. Wireless Compon Lett. vol.17, no.10, pp. 271-273, Oct-2007.
[2] A. M., Boon C. Chye, D. M. Anh, and Y. K. Seng, “A 3–8 GHz Low-Noise CMOS Amplifier”, IEEE Microw. Wireless Compon Lett. vol.19, no.4, pp. 245-247, April-2009.
[3] M.T. Reiha and J. R. Long, “A 1.2V Reactive-Feedback 3.1- 10.6 GHz Low-Noise Amplifier in 0.13µm CMOS”, IEEE J. Solid State Cricuits, vol.42, no.5, pp. 1023-1033, May. 2007.
[4] C.-C. Chiong, D.-J. Huang, C.-C. Chuang, Y. -J. Hwang, M.-T. Chen and H. Wang, “Cryogenic 8-18 GHz MMIC LNA using GaAs PHEMT”, IEEE Asia-Pacific Microw. Conf., 2013, pp. 261-263.
[5] H. L. Kao, C. S. Yeh, C. L. Cho, B. W. Wang, P. C. Lee, B. H. Wei, and H. C. Chiu, “Design of an S-band 0.35 μm AlGaN/GaN LNA using Cascode Topology”, Int. Symp. on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, pp. 250-253, 2013.
[6] A. Seyfollahi , N. Jiang , J. Bornemann , L. B. G. Knee , D. Garcia and P. Niranjanan , “Full-Wave Analysis and Design of a Wideband GaAs pHEMT MMIC LNA,”IEEE Int. Symp. on Antenna Tech. and Applied Electromagnetics (ANTEM) , 2018, pp. 1-5.
[7] Y.-Y. Peng, et al., “A low power S-band receiver using GaAs pHEMT technology,” in IEEE 13th ISIC Symp. Dig., Dec., 2011.
[8] J.-C. Guo , C.-Sh. Lin and Y.-T. Liang, “Low voltage and low power UWB CMOS LNA using current-reused and forward body biasing techniques”, in 2017 IEEE MTT-S Int. Microw. Symp., June 2017, pp. 764-767.
[9] M. Parvizi , K. Allidina and M. N. El-Gamal, “A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique,”IEEE Trans. on Very Large Scale Int. (VLSI) Systems, 2015, pp. 1111-1122.
[10] G. Sapone and G. Palmisano, “A 3–10-GHz low-power CMOS low-noise amplifier for ultra-wideband communication,” IEEE Trans. Microw. Theory Techn, vol. 59, no. 3, pp. 678–686, Mar. 2011.
[11] Y. Chen,Y.-H. Lin,C.-C. Chiong and H. Wang, “A 0.38-V, Sub-mW 5-GHz Low Noise Amplifier with 43.6% Bandwidth for Next Generation Radio Astronomical Receivers in 90-nm CMOS ”, in 2018 IEEE MTT-S Int. Microw. Symp., June 2018, pp. 1491-1494.
[12] Y.-C. Chen ,Y. Wang , C.-C. Chiong and H. Wang, “An ultra-broadband low noise amplifier in GaAs 0.1-μm pHEMT process for radio astronomy application,” IEEE Int. Symp. on Radio-Frequency Int. Tech.(RFIT) , 2017, pp.80-82.
[13] J. Hu , K. Ma , S. Mou and F. Meng, “Analysis and Design of a 0.1-23 GHz LNA MMIC Using Frequency-Dependent Feedback,”IEEE Trans. Circuits and Syst. II, Exp. Briefs, Early Access, 2019.
[14] B. Razavi, RF Microelectronics, 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2011.
[15] M. Daoud , R. Aloulou , H. Mnif , M. Ghorbel, “Inductive Degeneration Low Noise Amplifier for IR-UWB Receiver for Biomedical Implant,” IEEE 27th Int. Conf. on Micro. (ICM), Dec. 2015, pp. 95–98.
[16] X. A. Nghiem, J. Guan, and R. Negra, “Design of a broadband three-way sequential Doherty power amplifier for modern wireless communications,” in IEEE MTT-S Int. Microw. Symp. Dig., 2014 pp. 1–4.
[17] H.-W. Lei ; Y. Wang ; C.-C. Chiong and H. Wang,“A 2.5-31 GHz High Gain LNA in 0.15-µm GaAs pHEMT for Radio Astronomical Application”, IEEE Asia-Pacific Microw. Conf., Nov. 2018, pp. 228-230.
[18] T. Y .Yang, Li-C Pai, and H .K . Chiou, “A compact Ka-Band Power Amplifier using finite-ground coplanar waveguide design” in IEEE Asia-Pacific Microw. Conf., 2005.
[19] J. H. Tsai and T. W. Huang, "A 38-46 GHz MMIC Doherty power amplifier using post-distortion linearization," in IEEE Microw. Wireless Compon. Lett. vol. 17, no. 5, pp. 388-390, May 2007.
[20] A. Agah, et. al., "Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS," IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2338- 2350, Oct. 2013.
[21] S. Hu, F. Wang, and H. Wang, “A 28 GHz/37 GHz/39 GHz multiband linear Doherty power amplifier for 5G massive MIMO applications,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 32–33.
[22] D. Kim, H. Park, S. Eom, J. Jeong, H. Cha, and K. Seo, "KaBand MMIC Using AlGaN/GaN-on-Si With Recessed High-k Dual MIS Structure," IEEE Electron Device Letters, vol. 39, no. 7, pp. 995-998, 2018.
[23] R. G. Freitag, “A Unified Analysis of MMIC Power Amplifier Stability”, MlT-S Int.l Microw. Symp. Dig. 1992.
[24] Y. C. Lee and C. S. Pard, “17–36 GHz broadband PHEMT MMIC power amplifier for point-to-multipoint applications,” in Proc. Int.Conf. Solid-State and Integrated Circuits, 2001, vol. 2, pp. 1320–1323.
[25] Y. Sasaki, H. Kurusu, H. Hoshi, T. Hisakaa, and Y. Mitsui, “20–30GHz broadband MMIC power amplifiers with compact flat gain PHEMT cells,” in IEEE Int. Micro. Symp. Dig., 2001, vol. 2, pp.1067–1070.
[26] Y.A. Lin ; J.R. Ji ; T.H. Chien ; H.Y. Chang and Yu-Chi Wang, “A Ka-band 25-dBm output power high efficiency monolithic Doherty power amplifier in 0.15-μm GaAs E-mode pHEMT process”, IEEE Asia-Pacific Microw. Conf, pp. 984-987, 2017.
[27] H.Yu.Lin and W.T.Li, “A Ka-Band Power Amplifier with Phase Compensation Technique Applied to 5G Phased Array”, IEEE Asia-Pacific Microw. Conf, pp. 61-63, 2018.
[28] B. Park et al., "Highly Linear mm-Wave CMOS Power Amplifier," IEEE Trans. Microw. Theory Tech., vol. 64, no. 12, pp. 4535-4544, Dec. 2016
[29] S. Shakib, H. C. Park, J. Dunworth, V. Aparin and K. Entesari, "20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, 2016, pp. 352-353.
[30] P. C. Huang, Z. M. Tsai, K. Y. Lin, and H. Wang, “17–35 GHz broadband, high efficiency pHEMT power amplifier using synthesized transformer matching technique,” in IEEE MTT, 2012, vol. 60, pp. 112-119.
[31] A. Bessemoulin, H. Massler, A. Hulsmann and M. Schlechtweg” Ka-band high-power and driver MMIC amplifiers using GaAs PHEMTs and coplanar waveguides”, IEEE Microw. and Guided Wave Lett., Dec. 2000.
[32] D. P. Nguyen, T. Pham, B. L. Pham, and A.-V. Pham, “A high efficiency high power density harmonic-tuned Ka-band stacked-FET GaAs power amplifier,” in Proc. IEEE Compound Semiconductor Integr. Circuit Symp. (CSICS), Oct. 2016, pp. 1–4.
[33] D. P. Nguyen, A. Pham, "An ultra compact watt-level Ka-band stacked-FET power amplifier," IEEE Microw. Wireless Comp. Lett., vol.26, no.7, pp. 516-518, July 2016.
[34] C. W. Kuo, H. K. Chiou and H. Y. Chung, "An 18 to 33 GHz Fully-Integrated Darlington Power Amplifier WithGuanella-Type Transmission-Line Transformers in 0.18 m CMOS Technology," IEEE Microw. Wireless Compon. Lett., vol. 23, no. 12, pp. 668-670, Dec. 2013
[35] M. Balducci, S. Chartier and H. Schumacher, "A Ka-band low power and high-efficiency differential power amplifier in 0.25-µm BiCMOS”, in INMMIC, Graz, 2017, pp. 1-3.
[36] C. H. Tsay, J. C. Kao, K. Y. Kao and K. Y. Lin, "A 27–34 GHz CMOS medium power amplifier with a flat power performance," in IEEE Asia-Pacific Microw. Conf, Kaohsiung, 2012, pp. 1-3
[37] A.Vasylyev, P. Weger, and W. Simburger, “Ultra-broadband 20.5–31 GHz monolithically-integrated CMOS power amplifier,” Electron. Lett., vol. 41, no. 23, pp. 1281–1282, Nov. 2005.
[38] S. Li, D. Fritsche, C. Carta and F. Ellinger, "Design and characterization of a 12–40 GHz power amplifier in SiGe technology," 2018 IEEE Topical Conf. on RF/Microw. Power Amplifiers for Radio and Wireless Applications (PAWR), Anaheim, CA, 2018, pp. 23-25.
[39] J.-W. Lee and S.-M. Heo, “A 27 GHz, 14 dBm CMOS power amplifier using 0.18 common-source MOSFETs,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 11, pp. 755–757, Nov. 2008.
[40] 黃暄尹「使用T模型匹配網路之寬頻氮化鎵功率放大器暨金氧半場效應電晶體功率放大器設計及砷化鎵低雜訊降頻器之研製」，國立中央大學，碩士論文，民國 106年。
[41] 簡子涵「W頻帶40奈米金氧半場效應電晶體低雜訊放大器暨Ka頻帶砷化鎵功率放大器之研製」，國立中央大學，碩士論文，民國 107年。
[42] C.-H. Wu, and N.-Y. Wu, “Design of low power up-conversion self-oscillating mixer,” in Proc. China-Japan Joint Microw. Conference, (CJMW) pp. 1–4, Apr. 2011
[43] C.-H. Wu, and G.-X. Jian, “Design of up conversion mixer with enhanced transconductance stage and low power consumption oscillator,” in Proc. Int. Conf. on Signals and Electronic Systems, pp. 229–232, Sept. 2010.
[44] K. W. Kobayashi, A. K. Oki, D. K. Umemoto, T. R. Block, and D. C. Streit, “A novel self-oscillating HEMT–HBT cascode VCO-mixer using an active tunable inductor,” IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 1231–1240, Jun. 1998.
[45] J.-Y. Kim; W.-Y. Choi, “30 GHz CMOS self-oscillating mixer for self-heterodyne receiver application,” IEEE Microw. Compon. Lett., vol. 20, no. 6, pp. 334–336, June. 2010.
[46] F. Starzer, P.-H. Forstner, L. Maurer, and A. Stelzer, “A 21-GHz self-oscillating down-converter mixer,” 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF systems (SiRF), Jan. 2012, pp. 93–96.
[47] Z. Li ; J. Cao ; Q. Li and Z. Wang, “A wideband Ka-band receiver front-end in 90-nm CMOS technology,” IEEE European Microw. Integrated Circuit Conf. , pp. 5–8, Dec. 2013.
[48] S. S. H. Hsu ; P.-Yi Wang ; P.-Ch. Su ; M.-C. Chou ; Y.-C. Chang and Da-C. Chang, “Design of Ku/Ka band down-converter front-end for digital broadcast satellite receivers,” IEEE Int.Wireless Symp. (IWS). , pp. 1–4, Jul. 2015.
[49] M. Vidojkovic ; V. Vidojkovic ; M. A. T. Sanduleanu ; J. v. d. Tang ; P. B. and A.r v. Roermund, “A 1.2V inductorless receiver front-end for multi-standard wireless applications,” IEEE Radio and Wireless Symp.. , pp. 41–44, Mar. 2008.
[50] Y-Chen;Z.-I Yu ; C.-Y. Huang ; K.-H. Hsieh and R.-Hu, “Design of 18-26 Receiver with Wideband RF,LO and IF in 0.15-μm GaAs pHEMT process”, IEEE Asia-Pacific Microw. Conf, IEEE, pp. 1250-1253, 2017.
[51] K.-C. Lin ; H.-K. Chiou ; K.-H. Chien ; T.-Y. Yang ; P.-C. Wu ; C.-L. Ko and Y.-Z. Juang, “A 4.2-mW 6-dB Gain 5–65-GHz Gate-Pumped Down-Conversion Mixer Using Darlington Cell for 60-GHz CMOS Receiver,” IEEE Trans.Microw. Theory Techn, vol. 61, no. 4, pp. 1516–1522, Mar. 2013.
[52] K. Kanaya , K. Kawakami , T. Hisaka , T. Ishikawa , and S. Sakamoto, “A 94 GHz high performance quadruple subharmonic mixer MMIC,” IEEE Trans.Microw. Theory Techn, pp. 1249–1252, Aug. 2002.
[53] D. Dawn, S. Sarkar, P. Sen, B. Perumana, D. Yeh, S. Pinel, and J. Laskar, “17-dB-Gain CMOS Power Amplifier at 60GHz”, IEEE Int. Microw. Symp. Dig., pp 859-862, Jun. 2008.
[54] T. Yao, et al., “Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio”, IEEE J. Solid-State Circuits, vol. 42, No. 5, pp. 1044-1057, May 2007.
[55] D. Chowdhury, et al., “A 60GHz 1V +12.3dBm Transformer-Coupled Wideband PA in 90nm CMOS”, ISSCC Dig. Tech Papers, pp 560-561, Feb., 2008.
[56] J.-J. Lin, K.-H. To, H. D., K. B., M. M., Huang W.M., “Power Amplifier for 77-GHz Automotive Radar in 90-nm LP CMOS Technology,” IEEE Microw. Wireless Compon Lett, pp. 292 – 294, 2010.
[57] J.-H. Tsai, Y.-L. Lee, T.-W. Huang, C.-M. Yu and J. G.J.Chern “A 90-nm CMOS broadband and miniature Q-band balanced medium power amplifier,” 2007 IEEE MTT-S Int. Microw. Symp. Dig, pp.1129–1132. 2007.
[58] 陳穎「微波低功耗低雜訊放大器與毫米波Doherty功率放大器的設計」，國立台灣大學，碩士論文，民國 108年
[59] 穩懋PL15-12 0.15μm InGaAs pHEMT Power Device Layout Design Manual
[60] 穩懋PP10-10 0.1μm InGaAs pHEMT Power Device Layout Design Manual
[61] 穩懋PE15-00 0.15μm InGaAs pHEMT Power Device Layout Design Manual