動態隨機存取記憶體在許多電子系統中為一個關鍵元件，為維持其資料完整性，動態隨機存取記憶體必須執行週期性的復新動作，然而復新動作本身卻是一個非常耗能的動作。另一方面，動態隨機存取記憶體會受到軟性錯誤的影響而將會使其成為一個不可靠的元件。因此，動態隨機存取記憶體需要有效的節能及可靠度提升技術。
錯誤更正碼及硬體冗餘方法兩者皆為廣泛使用於提升可靠度及良率的技術。
在本論文中，一個混合式錯誤更正碼及硬體冗餘技術(Hybrid ECC and redundancy technique, HEAR)被提出用於降低動態隨機存取記憶體的復新功耗及提升其可靠度。在本文的第一部分，所提出的HEAR 技術被用於降低動態隨機存取記憶體待機時的復新功耗，該技術使用BCH 碼及錯誤位元修正模組來延展復新週期使得動態隨機存取記憶體的復新功耗得以被降低。透過結合BCH 碼及錯誤位元修正模組，所提出的混合式錯誤更正碼及硬體冗餘元件技術可以最小化錯誤更正碼所帶來的負面影響。分析結果表示所提出的技術可以節省2Gb DDR3 DRAM 40~70%的待機能量。檢查碼及錯誤更正碼電路的面積消耗只需為只使用錯誤更正碼策略時的63%及53%。
在本論文的第二部分中，HEAR 技術被用於動態隨機存取記憶體快取的可靠度提升。該技術可以更正動態隨機存取記憶體中的硬性錯誤及軟性錯誤。評估結果表示當使用可更正兩位元的錯誤更正碼及一位元的錯誤位元修正模組時其提供的可供的可靠度略低於兩位元錯誤更正碼及三位元錯誤更正碼，然而其效能花費僅為兩位元及三位元錯誤更正碼的0.125%。另一方面，三倍模組冗餘方法被用於更正快取的標籤即使這會將標籤複製成三份。整體的儲存空間花費被限制於12.5%，可靠度及效能花費都比單一位元錯誤更正碼效果更佳。

Dynamic random access memory (DRAM) is one key component in many electronic systems. To preserve the data integrity, DRAM needs to execute the refresh operation periodically. However, refresh operation is a power-hungry operation. On the other hand, DRAM is prone to soft errors such that it is an unreliable component in a system. Therefore, effective power-reduction and reliability-enhancement techniques are needed for DRAMs.
Error correction code (ECC) and hardware redundancy are widely used techniques for enhancing
the reliability and yield of DRAMs. In this thesis, we proposed a hybrid ECC and hardware
redundancy (HEAR) technique for reducing refresh power and enhancing reliability of DRAMs.

In the first part of this thesis, the proposed HEAR technique is used to reduce the refresh power
of DRAMs in standby mode. The HEAR technique uses a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to prolong the refresh period such that the refresh power of DRAM can be reduced. By combining BCH and EBR, the HEAR technique can minimize
the adverse effects caused by the ECC technique. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63% and 53% of that of the ECC-only, respectively.

In the second part of the thesis, a reliability-enhancement technique based on HEAR technique for DRAM caches is proposed. The reliability-enhancement technique can correct the hard errors and the soft errors in the DRAM cache. The evaluation result shows that when the configuration of the reliability-enhancement technique uses double error correction ECC and single bit repair, the provided reliability of the data part is close but slightly lower than that of double error correction or
triple error correction. However, the performance overhead can be only 0.125% of that of double error correction or triple error correction ECC at most. On the other hand, TMR is used to correct the tag part of the cacheline even though the tag is triplicated. The overall storage overhead for the DRAM cache is limited at 12.5%. Both reliability and performance overhead are more outstanding than single error correction ECC.

[1] J. Kim and M. C. Papaefthymiou, “Block-based multiperiod dynamic memory design for low dataretention
power,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp.
1006–1018, Dec. 2003.
[2] V. Sridharan, N. DeBardeleben, S. Blanchard, K. B. Ferreira, J. Stearley, J. Shalf, and S. Gurumurthi,
“Memory errors in modern systems: The good, the bad, and the ugly,” in Proc. of the Twentieth Int’l
Conf. on Architectural Support for Programming Languages and Operating Systems, Mar. 2015, pp.
297–310.
[3] V. Sridharan, J. Stearley, N. DeBardeleben, S. Blanchard, and S. Gurumurthi, “Feng shui of supercomputer
memory positional effects in DRAMand SRAMfaults,” in Proc. of the Int’l Conf. for High-
Performance Computing, Networking, Storage, and Analysis, Nov. 2013, pp. 1–11.
[4] P. J. Nair, D.-H. Kim, and M. K. Qureshi, “Archshield: architectural framework for assisting DRAM
scaling by tolerating high error rates,” in Proc. of the 40th Annual Int’l Symp. on Computer Architec-
ture, Jun. 2013, pp. 72–83.
[5] Micron, “DDR3 SDRAM,” http://www.micron.com/∼/media/Documents/Products/Data%20Sheet/DRAM
/1Gb DDR3 SDRAM.pdf.
[6] W. A.Wulf and S. A.McKee, “Hitting the memory wall: implications of the obvious,” ACMSIGARCH
Computer Architecture News, vol. 23, no. 1, pp. 20–24, Mar. 1995.
[7] D. Jevdjic, G. H. Loh, C. Kaynak, and B. Falsaf, “Unison cache: A scalable and effective die-stacked
DRAM cache,” in IEEE/ACM Int’l Symp. on Microarchitecture, Dec. 2014, pp. 25–37.
[8] D. Jevdjic, S. Volos, and B. Falsaf, “Die-stacked DRAM caches for servers: Hit ratio, latency, or
bandwidth? have it all with footprint cache,” in Proc. of the 40th Annual Int’l Symp. on Computer
Architecture, Jun. 2013, pp. 404–415.
[9] X. Jiang, N. Madan, L. Zhao, M. Upton, R. Iyer, S. Makinen, and D. Newel, “CHOP: Adaptive filterbased
DRAM caching for CMP server platforms,” in IEEE 16th Int’l Symp’ on High Performance
Computer Architecture (HPCA), Jan. 2010, pp. 1–12.
[10] G. H. Loh, “Extending the effectiveness of 3d-stacked DRAM caches with an adaptive multi-queue
policy,” in IEEE/ACM Int’l Symp. on Microarchitecture, Dec. 2009, pp. 201–212.
[11] G. H. Loh and M. D. Hill, “Efficiently enabling conventional block sizes for very large die-stacked
DRAM caches,” in IEEE/ACM Int’l Symp. on Microarchitecture, Dec. 2011, pp. 454–464.
[12] M. K. Qureshi and G. H. Loh, “Fundamental latency trade-off in architecting DRAM caches: Outperforming
impractical SRAM-tags with a simple and practical design,” in IEEE/ACM Int’l Symp. on
Microarchitecture, Dec. 2012, pp. 235–246.
[13] L. Zhao, R. Iyer, R. Illikkal, and D. Newell, “Exploring DRAM cache architectures for CMP server
platforms,” in Int’l Conf. on Computer Design, Oct. 2007, pp. 55–62.
[14] M. Ghosh and H.-H. S. Lee, “Smart refresh: an enhanced memory controller design for reducing
energy in conventional and 3D die-stacked DRAMs,” in IEEE/ACM International Symp. on Microar-
chitecture, Dec. 2007, pp. 134–145.
[15] Y. Idei, K. Shimohigashi, M. Aoki, H. Noda, H. Iwai, K. Sato, and T. Tachibana, “Dual-period selfrefresh
scheme for low-power DRAMs with on-chip PROM mode register,” IEEE Jour. of Solid-State
Circuits, vol. 33, no. 2, pp. 253–259, Feb. 1998.
[16] S. Takase and N. Kushiyama, “A 1.6-GByte/s DRAMwith flexible mapping redundancy technique and
additional refresh scheme,” IEEE Jour. of Solid-State Circuits, vol. 34, no. 11, pp. 1600–1606, Nov.
1999.
[17] R. K. Venkatesan, S. Herr, and E. Rotenberg, “Retention-aware placement in DRAM (RAPID): softwaremethods
for quasi-non-volatile DRAM,” in Intl Symp. on High-Performance Computer Architech-
ture, Feb. 2006, pp. 155–165.
[18] T. Ohsawa, K. Kai, and K.Murakami, “Optimizing the DRAMrefresh count for merged DRAM/Logic
LSIs,” in Intl Symp. on Low-Power Electronics and Design, Aug. 98, pp. 82–87.
[19] S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn, “Flikker: saving DRAM refresh-power
through critical data partitioning,” in Proc. of Intl Conf. on Architectural Support for Programming
Languages and Operating Systems, Mar. 2011, pp. 213–224.
[20] J. Liu, B. Jaiyen, R. Veras, and O. Mutlu, “RAIDR: retention-aware intelligent DRAM refresh,” in
Proc. of Intl Symp. on Computer Architecture, Jun. 2012, pp. 1–12.
[21] C. Wilkerson, A. R. Alameldeen, Z. Chishti, D. S. W. Wu, and S.-L. Lu, “Reducing cache power
with low-cost, multi-bit error- correcting codes,” in Proc. of Intl Symp. on Computer Architecture, Jun.
2010, pp. 83–93.
[22] P. Reviriego, A. Sanchez-Macian, and J. A. Maestro, “Low power embedded DRAM caches using
BCH code partitioning,” in IEEE Intl On-Line Testing Symposium (IOLTS), Jun. 2012, pp. 79–83.
[23] T. Nagai, M. Wada, H. Iwai, M. Kaku, A. Suzuki, T. Takai, N. Itoga, T. Miyazaki, H. Takenaka,
T. Hojo, and S. Miyano, “A 65nm low-power embedded DRAM with extended data-retention sleep
mode,” in IEEE Intl Solid-State Circuits Conf, Feb. 2006, pp. 567–576.
[24] P.-Y. Chen, C.-L. Su, C.-H. Chen, and C.-W. Wu, “Generalization of an enhanced ECC methodology
for low power PSRAM,” IEEE Trans. on Computers, Jun. 2012, (online).
[25] J.-H. Ahn, B.-H. Jeong, S.-H. Kim, S.-H. Chu, S.-W. Cho, H.-J. Lee, M.-H. Kim, S.-I. Park, S.-W.
Shin, J.-H. Lee, B.-S. Han, J.-K. Hong, P. B. Moran, and Y.-T. Kim, “Adaptive self refresh scheme for
battery operated high-density mobile DRAM applications,” in IEEE Asian Solid- State Circuits Conf.,
Nov. 2006, pp. 319–322.
[26] Y. Katayama, E. J. Stuckey, S.Morioka, and Z.Wu, “Fault-tolerant refresh power reduction of DRAMs
for quasi-nonvolatile data retention,” in Intl Symp. on Defect and Fault Tolerance in VLSI Systems, Nov.
1999, pp. 311–318.
[27] S.-S. Pyo, C.-H. Lee, G.-H. Kim, K.-M. Choi, Y.-H. Jun, and B.-S. Kong, “45nm low-power embedded
pseudo-SRAMwith ECC-based auto-adjusted self-refresh scheme,” in IEEE Intl Symp. on Circuits and
Systems (ISCAS), May 2009, pp. 2517–2520.
[28] P. G. Emma, W. R. Reohr, and M. Meterelliyoz, “Rethinking refresh: increasing availability and reducing
power in DRAM for cache applications,” IEEE Micro, vol. 28, no. 6, pp. 47–56, Nov.-Dec.
2008.
[29] A. Chakraborty, H. Homayoun, A. Khajeh, N. Dutt, A. Eltawil, and F. Kurdahi, “E ¡ mc2: Less energy
through multi-copy cache,” in Proc. of the 2010 Int’l Conf. on Compilers, architectures and synthesis
for embedded systems, Oct. 2010, pp. 237–246.
[30] H. Sun, N. Zheng, and T. Zhang, “Realization of l2 cache defect tolerance using multi-bit ecc,” in
IEEE Int’l Symp. on Defect and Fault Tolerance of VLSI Systems, Oct. 2008, pp. 254–262.
[31] A. R. Alameldeen, I. Wagner, and Z. Chishti, “Energy-efficient cache design using variable-strength
error-correcting codes,” in IEEE Int’l Symp. on Computer Architecture (ISCA), Jun. 2011, pp. 461–471.
[32] D. Roberts, N. S. Kim, and T. Mudge, “On-chip cache device scaling limits and effective fault repair
techniques in future nanoscale technology,” Microprocessors and Microsystems, vol. 32, no. 5-6, p.
244253, Aug. 2008.
[33] Z. Chishti, A. R. Alameldeen, C.Wilkerson,W.Wu, and S.-L. Lu, “Improving cache lifetime reliability
at ultra-low voltages,” in IEEE/ACM Int’l Symp. on Microarchitecture, Dec. 2009, pp. 89–99.
[34] L. D. Hung, M. Goshima, and S. Sakai, “Seva: A soft-error- and variation-aware cache architecture,”
in Pacific Rim Int’l Symp. on Dependable Computing (PRDC), Dec. 2006, pp. 47–54.
[35] W. Zhang, “Replication cache: A small fully associative cache to improve data cache reliability,” IEEE
TRANSACTIONS ON COMPUTERS, vol. 54, no. 12, pp. 1547–1555, Dec. 2005.
[36] S. Paul, F. Cai, X. Zhang, and S. Bhunia, “Reliability-driven ECC allocation for multiple bit error
resilience in processor cache,” IEEE TRANSACTIONS ON COMPUTERS, vol. 60, no. 1, pp. 20–34,
Jan. 2011.
[37] P. P. Shirvani and E. J. McCluskey, “Padded cache: A new fault-tolerance technique for cache memories,”
in IEEE VLSI Test Symposium, Apr. 1999, pp. 440–445.
[38] I. Koren and C. M. Krishna, “Fault-tolerant systems.” Morgan Kaufman Publishers Inc., San Francisco,
CA, USA, 2007.
[39] R. C. Bose and D. K. Ray-Chaudhuri, “On a class of error-correcting binary group codes,” Information
and Control, vol. 3, no. 1, pp. 68–79, Mar. 1960.
[40] J. Massey, “Shift-register synthesis and bch decoding,” IEEE Transactions on Information Theory,
vol. 15, no. 1, pp. 122–127, Jan. 1969.
[41] R. Chien, “Cyclic decoding procedures for bose- chaudhuri-hocquenghem codes,” IEEE Transactions
on Information Theory, vol. 10, no. 4, pp. 357–363, Oct. 1964.
[42] T.-H. Chen, “An adaptive-rate error correction scheme for NAND flash memory,” in master thesis,
National Tsing Hua University, Jul. 2008, pp. 1–83.
[43] Y. Choi, H. Jeong, and H. Kim, “Future evolution of memory subsystem in mobile applications,” in
IEEE Int’l Memory Workshop (IMW), 2010, pp. 1–2.
[44] W. R. Hamburgen, D. A. Wallach, M. A. Viredaz, L. S. Brakmo, C. A. Waldspurger, J. F. Barlett,
T.Mann, , and K. I. Farkas, “Itsy: stretching the bound of mobile computing,” IEEE Computer, vol. 34,
no. 4, pp. 28–36, Apr. 2001.
[45] M. A. Viredaz and D. A. Wallach, “Power evaluation of a handheld computer,” IEEE Micro, vol. 23,
no. 1, pp. 66–74, Jan/Feb 2003.
[46] T. Hamamoto, S. Sugiura, and S. Sawada, “On the retention time distribution of dynamic random
access memory(DRAM),” IEEE Transactions on Electron Devices, vol. 45, no. 6, pp. 1300–1309, Jun.
1998.
[47] R. C. Bose and D. K. Ray-Chaudhuri, “On a class of error-correcting binary group codes,” Information
and Control, vol. 3, no. 1, pp. 68–79, Mar. 1960.
[48] Semiconductor Industry Association, “International technology roadmap for semiconductors,” Seoul,
Korea, 2010.