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研究生： 鄭宇亨
Yu-Heng Cheng
論文名稱： 具資料獨立相位追蹤補償技術之10Gbps半速率時脈與資料回復電路
A 10 Gbps Half-Rate Clock and Data Recovery with Data Independent Phase Tracking Compensation Technique
指導教授： 鄭國興
Kuo-Hsing Cheng
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 中文
論文頁數： 133
中文關鍵詞： 時脈與資料回復電路 、鎖相迴路 、相位追蹤補償 、二進位相位偵測器
外文關鍵詞： Clock and Data Recovery (CDR), Phase Locked Loop (PLL), Phase Tracking Compensation, Bang Bang Phase Detector (BBPD)
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    • 隨著行動裝置、電腦網路以及半導體產業日益蓬勃發展，傳統並列傳輸已漸被串列傳輸所取代，並且資料傳遞的速率日漸提升。例如高速串列傳輸技術所使用之PCI-Express、SATA、USB或是光纖網路中的SONET等規格皆已採用串列傳輸作為介面，並且在最新世代規格中，資料傳輸速度甚至到達百億位元每秒等級，因此在電路設計複雜度上也大大提升。
    本論文參考USB 3.1 Gen2規格實現一個具資料獨立相位追蹤補償技術之半速率時脈與資料回復電路，並提出相位追蹤補償相位偵測器，針對傳統二進位相位偵測器在高速傳輸下之缺陷做改良。在高速傳輸下，追鎖資料相位變化能力及迴路延遲是影響時脈與資料回復電路效能的重要因素，當輸入資料有連續相同位元時傳統二進位相位偵測器無法判斷領先落後且輸出訊號最小脈波寬度會隨資料速率上升而縮小使得訊號完整度下降，此外，傳統二進位相位偵測器使用同步電路整合訊號邏輯，對減少迴路延遲是一大阻礙。而相位追蹤補償相位偵測器能在輸入資料有連續相同位元下亦能調整還原時脈相位，並使用輸入資料取樣還原時脈來除去同步電路緩解迴路延遲進而提升抖動容忍度。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程，操作電壓為1 V，輸入資料為10 Gbps PRBS7時，還原時脈速率為5 GHz，還原時脈之峰對峰值21.2 pspp，方均根值3.3 psrms，功率消耗為30.1 mW，晶片面積為1.59 mm2，核心電路面積為0.154 mm2。

    In recent years, according to the rapid development of the process and computers, the series data transmission is widely used for the bus instead of the parallel transmission and the data rate increases progressively, such as PCI-Express, SATA, USB and SONET in the fiber network. The data rate has even risen up to ten billion bits per second in the latest generation specifications. Therefore, the circuit design complexity is greatly increased.
    This thesis presents a clock and data recovery (CDR) with a data independent phase tracking compensation technique which takes the USB 3.1 Gen2 specification as a reference material. The proposed CDR presents a phase tracking compensation phase detector (PTCPD) which improved the drawback of the conventional bang-bang phase detector (BBPD) in high-speed transmission. When input data has long run situation, the BBPD can’t determine leading or lagging and the minimum pulse width of BBPD output signal will decrease with the increasing of data transmission rate. Above situation will degrade the jitter tolerance (JTOL) and the signal integrity. In addition, the BBPD needs re-timing circuit to integrate signal logic which is an obstacle for reducing the loop latency. The PTCPD can adjust the recovered clock phase in long run situation and use input data sampling recovered clock to remove the re-timing circuit which make JTOL enhanced. The chip is fabricated by a 90 nm standard CMOS process with a supply voltage of 1 V and the input data is 10 Gbps PRBS7 pattern. The measured jitter of the recovered clock is 3.3 psrms, 21.2 pspp, the chip area is 1.59 mm2, the core area is 0.154 mm2 and the total power consumption is 30.1 mW.

    摘要 i Abstract ii 誌謝 iii 目錄 v 圖目錄 x 表目錄 xiv 第1章 緒論 1 1.1 研究動機 1 1.2 論文架構 4 第2章 高速串列傳輸之訊號完整性 5 2.1 基本觀念 5 2.1.1 隨機二元資料之型態 5 2.1.2 隨機二元資料之特性 6 2.1.3 資料編排形式 7 2.2 時脈抖動簡介 8 2.2.1 隨機性抖動(Random Jitter, RJ) 9 2.2.2 定量性抖動(Deterministic Jitter, DJ) 10 2.2.2.1 資料相關抖動(Data Dependent Jitter, DDJ) 10 2.2.2.2 責任週期失真(Duty Cycle Distortion, DCD) 11 2.2.2.3 週期性抖動(PJ) 12 2.2.3 抖動量測的方法 13 2.2.3.1 時間間隔誤差(Time Interval Error, TIE) 14 2.2.3.2 週期抖動(Period Jitter) 15 2.2.3.3 循環抖動(Cycle-to-cycle Jitter, C2C Jitter) 16 2.2.3.4 抖動量測方法之總結 17 2.3 眼圖分析 18 2.4 誤碼率 19 2.5 相位雜訊理論 20 2.5.1 Leeson 相位雜訊模型(Linear Time Invariance, LTI)[18]-[19] 21 2.5.2 Hajimiri相位雜訊模型(Linear Time Variance, LTV)[20]-[23] 23 第3章 時脈與資料回復電路之背景簡介 29 3.1 時脈與資料回復電路簡介 29 3.1.1 相位偵測器型態 30 3.1.2 取樣速率 31 3.1.3 抖動轉移函數(Jitter Transfer, JTF) 32 3.1.4 抖動容忍度(Jitter Tolerance, JTOL) 33 3.2 傳統時脈與資料回復電路 34 3.2.1 鎖相迴路式時脈與資料回復電路[26]-[27] 34 3.2.2 混合鎖相迴路/延遲鎖相迴路式時脈與資料回復電路[28]-[29] 36 3.2.3 超取樣式時脈與資料回復電路[30] 37 3.2.4 相位選擇式時脈與資料回復電路[31] 38 3.2.5 突發模式時脈與資料回復電路[32] 39 3.2.6 雙路徑式時脈與資料回復電路[33] 40 3.3 提升抖動容忍度之設計背景 41 3.3.1 多增益路徑之超取樣式時脈與資料回復電路[35]-[37] 41 3.3.2 自適應迴路增益之時脈與資料回復電路[24]、[38]-[39] 42 3.4 比較與討論 44 第4章 具資料獨立相位追蹤補償技術之時脈與資料回復電路設計與實現 47 4.1 電路架構 47 4.2 系統分析 49 4.2.1 頻率資訊鎖相迴路系統分析 49 4.2.2 時脈與資料回復電路系統分析 52 4.3 操作說明 58 4.3.1 高速傳輸下之非理想效應 58 4.3.1.1 抖動量佔資料位元週期之比例 58 4.3.1.2 資料訊號低轉態密度對二進位相位偵測器之影響 59 4.3.1.3 有迴路延遲下時脈與資料回復電路之追鎖情況與分析 60 4.3.2 相位追蹤補償相位偵測器分析 62 4.3.3 極限追鎖下相位偵測器輸出最小脈波寬度之比較 63 4.4 行為模擬 65 4.5 子電路介紹 67 4.5.1 半速率二進位相位偵測器 67 4.5.2 相位追蹤補償相位偵測器 70 4.5.3 利用電容放大技術之迴路濾波器 72 4.5.4 相位頻率偵測器 73 4.5.5 電荷幫浦 74 4.5.6 電壓控制振盪器 76 4.5.7 除頻器 78 4.5.8 擺幅轉換電路 79 4.6 模擬結果 79 4.6.1 操作在5 GHz之鎖相迴路模擬 80 4.6.1.1 佈局前模擬 80 4.6.1.2 佈局後模擬 81 4.6.1.3 閉迴路相位雜訊模擬 82 4.6.2 操作在10 Gbps之半速率時脈與資料回復電路模擬 83 4.6.2.1 佈局前模擬 83 4.6.2.2 佈局後模擬 85 4.6.3 抖動容忍度模擬 87 第5章 晶片佈局與量測 89 5.1 電路佈局 89 5.1.1 晶片封裝 90 5.1.2 佈局與電源規劃 92 5.2 量測考量 93 5.2.1 量測環境 93 5.2.2 印刷電路板 94 5.2.3 高頻輸出緩衝器 95 5.2.4 低頻輸出緩衝器 96 5.2.5 高頻輸入端 97 5.3 晶片與印刷電路板照相 98 5.4 量測結果 99 5.4.1 頻率資訊鎖相迴路量測 99 5.4.2 時脈與資料回復電路量測 101 5.4.2.1 相位追蹤補償相位偵測器 101 5.4.2.2 傳統二進位相位偵測器 102 5.4.3 量測結果分析 103 5.4.4 抖動容忍度量測 104 5.5 規格比較表 106 第6章 結論 109 6.1 結論 109 6.2 未來研究方向 – 動態最佳化抖動容忍度調整 110 參考文獻 111

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