本論文主要是研究一個省記憶體空間和省計算時間的一維雙載子接面電晶體模型並且驗證它與傳統二維雙載子接面電晶體模型的元件特性是相當接近。研究的方法是採用等效電路法(equivalent circuit approach)。所謂的等效電路法就是將半導體元件的柏松方程式、電子連續方程式以及電洞連續方程式轉換成等效電路。在矩陣解法器部份，我們以帶狀式矩陣解法器(Band Matrix Solver)取代一般的滿狀式矩陣解法器(Full Matrix Solver)來解決二維元件模擬中所需要大量矩陣空間的問題。但為了研究一個有效率的雙載子接面電晶體模型，我們還是需要以一維雙載子接面電晶體模型取代傳統二維雙載子接面電晶體模型。在一維雙載子接面電晶體模型的研究中，我們已經克服了在基極端的邊界條件問題而且也驗證了其特性確實與二維雙載子接面電晶體接近。所以我們應用這一維雙載子接面電晶體模型在一些常見的元件與電路的混階模擬並且從中學習這些應用電路的工作原理。

In this thesis, we study on a 1D BJT model, which saves the memory size and computation time and verify that the characteristic of 1D BJT model is in good agreement with 2D BJT model. We use the equivalent circuit approach in this thesis. Poisson’s equation and continuity equations for electron and hole are formulated into a subcircuit format suitable for general circuit simulator in the equivalent circuit approach. In order to solve the 2D device simulation, the band matrix solver will replace the full matrix solver in this thesis. Because the 2D BJT simulation still needs a large computation time, the efficient 1D BJT model must be developed. In 1D BJT simulation, we have overcome the base boundary condition and verified that the base boundary conditions in 1D BJT model closely approach to that in 2D BJT model. Finally, we apply it to two applications and study the operation concepts of these applications.

[1] K. Mayaram and D. O. Pederson, “Coupling Algorithms for Mixed-level Circuit and Device Simulation,” IEEE Transactions on computer-aided design, vol. 11, no. 8, pp. 1003-1010, 1992.
[2] K. Mayaram and D. O. Pederson, “CODECS: A Mixed-level Device and Circuit Simulation,” in Proc. IEEE Int. Conf. Computer-aided Design, pp. 813-820, Nov. 1987.
[3] C.-L. Teng, “An Equivalent Circuit Approach to Mixed-Level Device And Circuit Simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 1997.
[4] M.-K. Tsai, “An Improved Levelized Incomplete LU Method And Its Application to 2D Semiconductor Device Simulation,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2000.
[5] L. L. Liou and C. I. Huang, “Using Constant Base Current at a Boundary Condition for One-Dimensional AlGaAs/GaAs Numerical Heterojunction Bipolar Transistor Simulation,” Electronics Letters, vol. 26, pp. 1501-1503, 1990.
[6] S.-F. Wang, “Comparison of One-Dimensional and Two-Dimensional Simulation in Bipolar Transistors,” M. S. Thesis, Institute of EE, National Central University, Taiwan, Republic of China, Jun. 2000.
[7] H. C. Casey, jr., Devices for Integrated Circuits, Silicon and III-V Compound Semiconductors, Chapter 9, John Wiley & Sons, Inc., 1999.
[8] S. M. Kang, Y. Leblebici, CMOS Digital Integrated Circuit: Analysis And Design, Chapter 8, McGRAW-Hill, 1996.
[9] C. K. Alexander, and M. N. O. Sadiku, Fundamentals of Electric Circuits, Chapter 8, McGRAW-Hill, 2000.
[10] A. Mahmood, D. J. Lynch, and L. D. Philipp, “ A Fast Banded Matrix Inversion Using Connectivity of Schur’s Complements,” Systems Engineering, IEEE International Conference, pp. 303 —306, 1991.
[11] E. G. Friedman, “Latching Characteristics of a CMOS Bistable Register,” IEEE Transactions on Circuits and Systems-I, vol. 40, pp. 902-908, Dec., 1993.
[12] C. Y. Wu, H. D. Sheng, and Y. T. Tsai, “The Lambda Bipolar Phototransistor-Analysis and Applications,” IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 1227-1234, Dec., 1985.