應用於高階液晶顯示器並具壓縮率控制之高速無失真/失真嵌入式影像壓縮編解碼器

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研究生：	李侑豫 Yu-yu Lee
論文名稱：	應用於高階液晶顯示器並具壓縮率控制之高速無失真/失真嵌入式影像壓縮編解碼器 A High-Speed Lossless/Lossy Embedded Image Compression Codec with Rate Control Mechanism for High-End LCD Applications
指導教授：	蔡宗漢 Tsung-han Tsai
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
畢業學年度：	96
語文別：	英文
論文頁數：	60
中文關鍵詞：	嵌入式壓縮、影像壓縮、高速編解碼器、無失真/失真、壓縮率控制
外文關鍵詞：	image compression, lossless/lossy, high speed codec, rate control, embedded compression
相關次數：	點閱：6 下載：0
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由於高畫質LCD顯示面版技術的發展，高顯示規格的影像需求已是不可或缺的。因此使得LCD相關應用中，對資料速率及外部記憶體的頻寬、存取資料消耗的功率和儲存空間的需求大幅上升。本論文提出了高速並具有效率的嵌入式影像編解碼核心，可即時針對高解析度、高幀數的影像資料做壓縮，使得存取影像時所需之頻寬和消耗的功率下降。本論文提出了支援失真卅無失真的影像壓縮演算法，並且在失真模式下附加了可針對特定的壓縮率控制資料量的機制。因此可使得系統對外部記憶體儲存空間的需求大幅下降。此機制可以針對特定的壓縮率，適應性地根據影像內容來調整量化參數，因此在影像品質及壓縮效率上可以得到良好的平衡。
　　為了要處理高畫質顯示規格，在演算法開發之際就已考慮到硬體架構設計效能。在以硬體執行效率為主的前提下，本設計仍然維持良好的編碼效率。在硬體架構方面，提出的編解碼器透過有效率的資料排程和管線化技巧來提升處理速度並提供了平行編解碼的能力。本設計以TSMC 0.18um製程和Artisan cell library實現，在雙倍平行的架構下，其最高吞吐率可達 744 Mbyte/sec，功率消耗為 226mW@186MHz，core size為1.58x1.58 mm2，die size為2.06x2.07mm2。本論文所提出的編解碼器的處理能力可以完全涵蓋Full-HD 1080p@60Hz，且包含RGB色彩資料。與其它的設計相比，本設計在資料吞吐及功率消耗上皆更有效率，並且在使用的面積及儲存上的成本也較低。更進一步的，本設計擁有彈性增加平行度的能力。因此可用增加硬體份數的方式來因應更高的顯示規格，如QHD及QFHD。

Due to the great evolution of LCD panel technology, the requirement for image in high-definition has been indispensable.　Thus, for high-end LCD applications, the demands of data rate, memory bandwidth, and access power are drastically increased. With the proposed high speed and efficient embedded image compression codec, the data of image with high resolution and frame rate can be encoded or decoded in real time. Hence the memory bandwidth and the access power can be reduced. The image compression algorithm with lossless/lossy mode is proposed in this paper. With a rate control mechanism in lossy mode, the size of image data is assured. Hence the required capacity of external memory can be greatly reduced. For a target compression ratio, the rate control mechanism adaptively adjusts the quantization parameter according to the image content, and thus a good trade-off can be achieved between visual quality and coding efficiency.
In order to deal with image data in high-definition, the algorithm is designed for VLSI-oriented and maintains a competitive coding efficiency. The proposed embedded compression codec utilizes techniques of efficient data scheduling and pipeline stages to improve processing speed, and image samples can be encode and decode in parallel. The proposed design is implemented in TSMC 0.18um technology with Artisan cell library. With two-level parallelism, the max throughput of 744 Mbyte/sec, power consumption of 226mW@186MHz, core size of 1.58x1.58 mm2, and die size of 2.06x2.07mm2 can be achieved. The proposed embedded codec is fully compatible for Full-HD 1080p@60Hz in RGB domain. In comparison with other existing works, the proposed design is well-behaved in throughput and power consumption, and the cost in area and storage device is reduced. Furthermore, with capacity of flexible parallelism, the hardware architecture can be improved for advanced display specifications, such as QHD and QFHD.

摘要……...………...………...………...………...…….....……...………………………	i
Abstract……………………………………………………………………………………	ii
誌謝……...………...………...………...………...………...………...………...………...	iii
Content……………………………………………………………………………………	iv
List of Figures……………………………………………………………………………..	vi
List of Tables………………………………………………………………………………	viii
Chapter 1	Introduction………………………………………………….……………	1
1.1		Motivation……………………………………………………..…………...	2
1.2		Thesis Organization……………………………………………...………	4
Chapter 2	Background……………………………………………………..………	5
2.1		Fundamental Concepts of FELICS Algorithm…………………….……….	6
2.2		The Description of Prediction Template…………………………...………	7
2.3		The Description of Intensity Distribution Model………………………….	8
2.4		The Description of Adjusted Binary Code…………………………………	9
2.5		The Description of Golomb-Rice Code……………………………………	10
Chapter 3	The Proposed VLSI-Oriented Lossless/Lossy FELICS Algorithm……	11
3.1		Problem Definition in Original FELICS Algorithm……………………….	12
3.2		Compact Adjusted Binary Code…………………………………………	15
3.3		Storage-Less Golomb-Rice Code………………………………………….	17
3.4		Lossy Mode with Rate Control Mechanism……………………………….	21
Chapter 4	The Proposed Auxiliary Techniques……………………………………..	25
4.1		Color Difference Pre-Processing………………………………….……….	26
4.2		Segment Scan Manner for Flexible Hardware Parallelism………………...	28
4.3		Code Length Adaptation in Golomb-Rice Code…………….……………..	32
Chapter 5	The Proposed VLSI Architecture………………..………………………	34
5.1		Design Strategy………………...…………………………………………..	35
5.2		Data Scheduling for Efficient Hardware Design.………………………….	36
5.3		The Description of System Architecture…………………………………...	40
5.4		The Description of Primary Modules……………………………….……..	41
Chapter 6	Experiment Results and Analysis………………..………………………	49
6.1		Design and Verification Strategy………………………………………...	50
6.2		Coding Efficiency………………………………………………………….	51
6.3		Hardware Performance Evaluation……………………………...…………	54
Chapter 7	Conclusions……………………...………………..……………………….	57
References…………………………………………………………………………………	59

                                

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