快閃記憶體製程中蝕刻氮化矽產生之矽酸鹽在二氧化矽表面的沉積:質傳限制

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研究生：	鄧凱文 TENG KAI WEN
論文名稱：	快閃記憶體製程中蝕刻氮化矽產生之矽酸鹽在二氧化矽表面的沉積:質傳限制 Deposition of silicate from Si3N4 etching onto SiO2 surfaces in flash memory manufacturing: mass transfer limitation
指導教授：	曹恆光 HENG KWONG TSAO
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 化學工程與材料工程學系 Department of Chemical & Materials Engineering
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	31
中文關鍵詞：	蝕刻、氮化矽、磷酸、半導體
外文關鍵詞：	etch, silicon nitride, phosphoric acid, semi conductor
相關次數：	點閱：11 下載：0
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在3D NAND 快閃記憶體晶片中的氮化矽層通常用熱磷酸來去除。然而，蝕刻氮化矽所產生的矽酸鹽產物所造成在二氧化矽層上異常的沉積行為將會對接下來的製程造成嚴重的影響。因此，我們製作了一個由兩個間隔80m的控片所形成的簡單系統來研究此沉積行為。為了瞭解此現象，不同因素的影響像是水含量(磷酸濃度)，以及攪拌程度的不同，將在此系統中被檢驗。我們發現，隨著水含量或者攪拌速率的增加，二氧化矽的沉積速率將隨之減少。實驗結果證實，在二氧化矽層的異常沉積現象是狹小空間中的化學沉積以及質傳兩個因素競爭所造成的結果。

The Si3N4 layers in a 3D NAND flash patterned wafer are generally removed by hot phosphoric acid. However, the abnormal deposition of silicate which is the byproduct from Si3N4 etching onto the neighboring SiO2 layers will cause a serious problem in the following process. In this work, the abnormal deposition phenomenon was investigated by a simple system containing a narrow gap (~80 um) between two blanket wafers. To understand the mechanism, the influences of various factors on the chemical etching dynamics were examined, including the water content and the extent of mechanical agitation. It is found that the growth rate of SiO2 decreases as the water content or the extent of agitation is increased. Our experimental results reveal that the abnormal growth on SiO2 layers is a consequence of the competition between chemical deposition and mass transfer in a confined space (reaction-diffusion system).

摘要    i
ABSTRACT    ii
誌謝    iii
LIST OF CONTENTS    iv
LIST OF FIGURES    v
CHAPTER 1 INTRODUCTION    1
CHAPTER 2 EXPERIMENT    4
2-1  Materials    4
2-2  Apparatus    4
2-3  Fabrication of the Si3N4/SiO2 dual-wafer system    5
2-4  Experimental details    5
CHAPTER 3 RESULT AND DICUSSION    6
3-1  Effect of the water content on the etching rate    6
3-2  Deposition of silicate and abnormal growth    11
3-3  Agitation and mass transfer limitation of silicate    17
CHAPTER 4 CONCLUSION    21
CHAPTER 5 REFERENCE    23


                                

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[5] Hong et al, Compositions for etching and methods of forming a semiconductor device, United States patent. US 8,940,182 B2 (2015).
[6] Yu et al, Method and system for improving wet chemical bath process stability and productivity in semiconductor manufacturing, United States patent. US 2009/0087929 A1 (2009).
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[9] Buttet et al, Alternative to H3PO4 for Si3N4 removal by using chemical downstream etching, Electrochem. Soc. Trans. 64.39 (2015): 1-9.

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