近年隨著超大型積體電路快速的演進，實體設計遇到的困難也越來越嚴重，在擺置階段是電子設計自動化流程中是非常重要的一個環節，需要考量諸多後續可能遇到的問題來決定標準電路元件的擺放位置，其中全域擺置的結果更深深地影響整個擺置階段的結果。
以前以線長最佳化當作考量會導致繞線階段的困難，因此現今許多全域擺置研究重點為可繞度問題，藉由預先考量可繞度使其降低後續繞線階段不可繞的情形發生。目前解析式擺置器（analytical placer）會先以線長最佳化為考量產生初始擺置，再考慮線長、密度（bin density）及可繞度做進一步的優化，其中主流的兩種解析擺置法為多層級（multi-level）解析擺置法與上限下限（upper and lower bound）解析擺置法。
本論文提出一個不同於以往思維的解析擺置法，針對網格密度與繞線擁擠度過高的網格（bin），分析周圍網格的密度與擁擠度，利用網格擴散的概念，慢慢地把網格內部的元件往外推出，得到較為平均分佈的擺置，並利用本論文提出的初始擺置、區分內部與外部連線點障礙物與動態調整網格大小等方法，降低峰值繞線擁擠度，改善可繞度，解決後續繞線階段的問題。

As the VLSI technology advances, the design complexity has increased rapidly and induces many problems in physical design. Placement, an important stage in electronic design automation, has to consider many issues to determine the placement of standard cells. During cell placement, the global placement results will greatly affect the results of the entire placement stage.
Previous wirelength-driven placement may cause high routing congestion or produce an unroutable placement. Therefore, most of the global placement focus on improving the routability. The quality of placement results will determine the difficulty of routing stage to complete the connection of all segments. State-of-the-art analytical placers guide their placement by a wirelength-driven initial placement, followed by optimizing the objective function consisted of wirelength, density and routability. Multi-level and upper and lower bound analytical placement are two major placement methods.
In this thesis, we propose a different analytical placement method to optimize routability. Using a ripple bin method to spread cells and to solve bin density and routing congestion problems. Besides, using a new initial placement, distinguishing inner and outer pin, and dynamic bin size adjustment methods to reduce peak routing congestion.

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