由基地台及感測節點所構成的無線感測網路已逐漸普及於我們的日常生活中。其中，於無線感測網路中擔任要角的感測節點在擁有諸多優點的同時，也受到不少限制，如計算能力的限制、記憶體空間限制及能源限制。也因以上限制，導致感測節點常為攻擊者攻擊的首要目標。

　　有鑑於此，遠程證實被提出以檢查感測節點是否遭攻擊者入侵。其作法為透過挑戰/回應協定達成。驗證者可藉由遠程證實檢查證實者的記憶體完整性，以達到其目的。在遠程證實中，亂數填充及耗時驗證機制皆必須採用。然而，若耗時驗證機制被使用於一規模較大的無線感測網路時，會因網路延遲而無法發揮其功效。因而有了硬體基礎之遠程證實的誕生。該遠程證實利用鑲嵌於感測節點的防竄改晶片作為一遠端的代理人進行時間的測量，並驗證該主計算平台之完整性，因此挑戰值及回應值應先被預先計算好，並存放於防竄改晶片上。

　　本提案將利用資訊隱藏的技術，將原先應儲存於防竄改晶片上的挑戰值及回應值改存放於主計算平台中的亂數填充區塊。藉此減少防竄改晶片的儲存負擔，並同時增加亂數填充區塊的使用率。

Wireless sensor network (WSN) composed of base station and sensor nodes has been widely applied in our daily lives, such as healthcare monitoring systems. The advantages of sensor nodes are optimized implementation and cost-efficient. However, these sensors have limited resources in computation, memory capacity, and energy. For the reasons given above, these sensors become attractive target for various security risks. A compromised sensor node will result in fake data delivery or private data disclosure. Therefore, a security mechanism used for detecting the trustworthiness of a sensor node is urgently desired.

Remote attestation scheme, an effective protection mechanism, has been proposed for detecting the trustworthiness of a sensor node. The remote attestation is based on challenge-response protocol. A verifier can verify the trustworthiness of a sensor node by attesting it's integrity of program memory. In remote attestation, both random padding and time-based detection approach are essential. However, in a large-scale WSN, time-based detection approach is susceptible to varying transmission delays. Therefore, many hardware-based remote attestation schemes depending on a tamper-proof chip have been proposed. The tamper-proof chip is employed to act as a remote agent, therefore, it must store challenge-response pairs for verifying the trustworthiness of the sensor node.

In this thesis, we propose a remote attestation with lightweight tamper-proof chip. With stenography that we applied, the chip does not need to store challenge-response pairs. The challenge-response pairs are randomly stored in platform while only the lightweight tamper-proof chip is aware of the memory locations of these challenge-response pairs.

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