隨著超大型積體電路(VLSI)的製程進入奈米(nanometer)世代，系統變得越來越複雜，晶片(Chip)的輸入輸出焊墊 (I/O Pads)的個數也隨之增加，而輸入輸出焊墊的擺放位置不僅會影響到封裝上的繞線結果，對晶片內部的壓降值(IR-Drop)也有所影響；目前的研究大多是將上述兩項問題分成封裝與實體設計流程兩步驟來個別處理，但這樣的方法不僅費時也耗成本，若能運用「晶片-封裝共同設計」的概念(Chip-Package Co-Design)，並且找到一個好的焊墊（Pad）擺放方式，不僅可以同時解決封裝上繞線的問題與晶片內部的問題，耗費設計成本及時程的問題也可隨之而解。
本論文即在「晶片-封裝共同設計方法」的概念上，提出「壅塞度為導向法」與「焊墊交換法」來同時解決封裝上的繞線壅塞度(Congestion)以及晶片內部壓降的問題；根據實驗結果證明，本論文所提出的方法確實可有效地同時解決上述的兩項問題，並適用於不同的測試電路上。

When semiconductor technology further scales into nanometer era, I/O-pad counts increase continually due to more and more function in chip. The locations of I/O pads not only affect the package design, but also change the noise inside the core. The traditional approaches solve these problems in package design flow and physical design flow respectively, which may have time-consuming and over-design problems. Using chip-package co-design method in pad assignment stage may be a practical approach to simultaneously solve these problems. A good pad assignment can improve the routing quality in packages and reduce the IR-drop in cores, which may solve the over-design problem and shorter the design cycle, too.
In this thesis, a chip-package co-design approach is proposed to reduce the routing congestion in packages. A pad switching algorithm is also proposed to control the routing congestion in packages and the IR-drop in cores at the same time. The experimental results of this work are encouraging. Compared with different approaches, our methodology reduces the routing congestion in packages and the IR-drop in cores simultaneously in all test circuits.

[1] International Technology Roadmap for Semiconductors (ITRS) 2003.
[2] http://eda.ee.ucla.edu/ppt/c_80.ppt
[3] http://www.amkor.com/enablingtechnologies/FlipChip/index.cfm
[4] Man-Fai Yu and Wei-Ming Dai, W. ” Single-layer fanout routing and routability analysis for ball grid arrays”, IEEE/ACM International Conference on Computer-Aided Design, pages 581–586, November 1995.
[5] Y. Kubo and A. Takahashi. “Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 25, NO. 4, pages 725–733, April 2006.
[6] T. Miyoshi, S. Wakabayashi, T. Koide, and N. Yoshida. ”An MCM Routing Algorithm Considering Crosstalk”, International Symposium on Circuits and Systems, pages 212–214, May 1995.
[7] M.M. Ozdal, D.F. Wong, and P.S. Honsinger. ”Simultaneously Escape-Routing Algorithms for Via Minimization of High-Speed Boards”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 27, NO. 1, pages 84–95, January 2008.
[8] N.L. Koren. ”Pin Assignment in Automated Printed Circuit Board Design”, 9th Workshop on Design Automation, pages 72–79, June 1972.
[9] L. Mory-Rauch. ”Pin Assignment on a Printed Circuit Board”, 15th Conference on Design Automation, pages 70–73, June 1978.
[10] T.D. Am, M. Tanaka, and Y. Nakagiri. ”An Approach to Topological Pin Assignment”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 3, NO. 3, pages 250–255, July 1984.
[11] T. Mitsuhashi and E.S. Kuh. “Power and Ground Network Topology Optimization for Cell Based VLSIs”, IEEE/ACM Design Automation Conference, pages 524–529, June 1992.
[12] X.D.S. Tan and C.J.R. Shi. “Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling”, IEEE/ACM Design Automation Conference, pages 550–554, February 2001.
[13] J. Singh and S.S. Sapatnekar. “Congestion-Aware Topology Optimization of Structured Power/Ground Networks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 24, NO. 5, pages 683–695, May 2005.
[14] A. Dubey. ”P/G Pad Placement Optimization: Problem Formulation for Best IR Drop”, International Symposium on Quality Electronic Design, pages 340–345, March 2005.
[15] K. Shakeri and J.D. Meindl. “Compact Physical IR-Drop Models for Chip/Package Co-Design of Gigascale Integration (GSI)”, IEEE Transactions of Electron Devices, VOL. 52, NO. 6, pages 1087–1096, June 2005.