基於IEEE P1901規格之PLC系統基頻內接收機設計｜國立中央大學博碩士論文系統

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研究生：	陳彥 Yen-Chen
論文名稱：	基於IEEE P1901規格之PLC系統基頻內接收機設計 Design of Digital Baseband Inner Receiver for PLC System Based on IEEE P1901 Specification
指導教授：	薛木添 Muh-Tian Shiue
口試委員:
學位類別：	碩士 Master
系所名稱：	資訊電機學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	中文
論文頁數：	124
中文關鍵詞：	電力線
外文關鍵詞：	PLC
相關次數：	點閱：12 下載：0
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電力線通訊 (PLC)，主要是透過電力線，將數據或資訊以數位訊號處理方法進行傳輸，因其可以直接使用既有的配電網路做為傳輸線路，不需進行額外佈線以及連接方便等使其具備最後一哩的優勢，但是因為傳輸環境的雜訊干擾以及通道衰減嚴重，使得在實際資料傳輸率方面與理想的情況會有很大的落差。因此如何解決電力線傳輸通道衰減以及抵抗雜訊干擾以提升傳輸效率，一直是各界研究的重點所在。
本論文針對IEEE P1901的標準設計一基頻內接收機，由於IEEE P1901標準內所制定的前導符元為512點，而傳送的data封包為4096點，因此為了得到相對應於各子載波的通道效應，我們必須由前導符元作通道估測與內插，另外由前導符元之間的相位差我們可以由演算法得到SCO的初始值以加速SCO收斂，在硬體實現上由於前導符元與data封包各為512點與4096點，因此我們需要512點的FFT架構以及4096點的FFT架構，因此本論文實現了可變點數的memorybase-FFT，並加入dynamic scaling演算法以減少硬體面積，在頻域等化器方面採用指數型LMS演算法，相較於傳統的LMS演算法有較快的收斂速度，但是如何得到準確的指數型通道增益卻是一個問題，因此本論文針對可調整增益的數位座標軸旋轉計算器 (MGC-CORDIC)，提出改良的通道估測與等化流程，可以達到更好的效能，並且在硬體方面可與其他硬體作資源共享，進一步減少硬體面積，在模擬方面我們使用C code模擬傳輸過程及傳輸中的不理想效應，並與FPGA結果進行驗證，在最後使用90nm製程技術完成晶片設計。

Power Line Communication (PLC) is mainly about the transmission of information or data based on digital signal processing method. By directly using existing power distribution network as the transmission network, this method has the advantage of the “last mile” due to convenient connection and no need for extra wiring. However, with the noise interference in the transmission environment and the severe attenuation along the channel, there could be a huge drop off between the actual data transmission rate and the ideal data transmission rate. Therefore, the researches in all fields have been focusing on how to solve the attenuation along the power line transmission channel and to improve transmission efficiency against noise interference.
In this dissertation a digital baseband receiver has been designed with respect to IEEE P1901 standard. In IEEE P1901 standard the preamble is set to be 512 points and the transmitted data packet is set to be 4096 points. Therefore, the channel interpolation must be conducted during the preamble in order to obtain the channel effect corresponding to each subcarrier. In addition, based on the phase difference between preambles the initial value of SCO can be obtained in order to accelerate the convergence of SCO. From the viewpoint of hardware realization, the FFT architectures of 512 points and 4096 points will be required according to the preamble and data packet with 512 points and 4096 points, respectively. In this dissertation the memorybase-FFT with variable points has been realized with the aid of dynamic scaling algorithm to reduce the hardware area. For the frequency domain equalizer, the exponential step size LMS algorithm has been adopted which leads to faster convergence than traditional LMS algorithm. Yet the problem is how to obtain the accurate exponential channel gain. Therefore, in this dissertation the improved channel estimation and equalization process with respect to the coordinate rotation digital computer with adjustable gain (MGC-CORDIC) have been proposed for better performance. In addition, the resource sharing mechanism with additional hardware has led to further reduction in hardware area. In order to verify the design by simulation, the C code has been used to simulate the transmission process and the undesirable effects during transmission, furthermore it has been also verified by the result of FPGA. In the end the chip design has been completed by 90 nm process technology.

摘要............................................................................................................................................i
Abstract.....................................................................................................................................ii
目錄......................................................................................................................................... iv
圖目錄......................................................................................................................................vi
表目錄.......................................................................................................................................x
第一章 緒論..........................................................................................................................1
1 前言..........................................................................................................................1
2 研究動機................................................................................................................. 2
3 論文架構................................................................................................................. 3
第二章 IEEE P1901標準和系統架構....................................................................................4
1 正交分頻多工調變介紹...........................................................................................4
1.1 OFDM 之數學模型....................................................................................5
1.2 循環字首....................................................................................................6
2  PLC系統架構..........................................................................................................7
3  IEEE P1901規格標準簡介.....................................................................................9
3.1 收發機系統架構........................................................................................9
3.2 傳輸參數及實體層封包格式..................................................................10
3.3 反快速傅利葉轉換調變方式..................................................................11
3.4 前導符元格式及產生方法......................................................................12
第三章 PLC同步與等化架構設計.......................................................................................13
1 符碼邊界同步.........................................................................................................13
1.1 符碼邊界偏移效應..................................................................................13
1.2 符碼邊界偏移估測..................................................................................15
2 取樣時脈同步.........................................................................................................19
2.1 取樣時脈偏移效應..................................................................................19
2.2 取樣時脈偏移估測..................................................................................21
3 LMS頻域等化器....................................................................................................23
3.1 直角座標系LMS頻域等化器..................................................................23
3.2 極座標系LMS頻域等化器......................................................................25
3.3 指數型增益和相角LMS頻域等化器......................................................27
4 結合取樣時脈同步與頻域等化器架構設計.........................................................30
4.1 自動增益控制和載波回復等化器..........................................................30
4.2 取樣時脈回復等化器..............................................................................32
4.3 結合取樣時脈同步與等化雙迴路架構..................................................33
第四章 結合通道估測與頻域等化器架構設計............................................................... 35
1 通道估測與通道內插........................................................................................... 35
1.1 通道估測…….…...............…................................................................ 35
1.2 數位內插器…….…...........…................................................................ 37
1.3 通道頻域內插…….…....……............................................................... 41
2 座標軸旋轉數位計算器....................................................................................... 49
2.1 向量模式.................................................................................................51
2.2 旋轉模式................................................................................................ 52
3 MGC頻域等化器.................................................................................................. 53
4 對數與反對數轉換器............................................................................................57
4.1 對數轉換器…….…...........…................................................................ 57
4.2 基於Least squares演算法之對數轉換器…….…............................... 59
4.3 反對數轉換器…….….......…................................................................ 62
5 改良型MGC頻域等化器.......................................................................................62
5.1 提出的通道估測與等化流程…….…...........….................................... 63
5.2 轉換器誤差分析…….…....................................................................... 66
5.3 改良型MGC CORDIC架構…….…...................................................... 68
5.4 通道估測誤差比較…….….......…........................................................ 70
第五章 PLC系統模擬與結果............................................................................................74
1 模擬環境................................................................................................................74
2 取樣時脈偏移與補償模擬結果............................................................................76
3 星座圖模擬結果....................................................................................................79
4 BER模擬結果.........................................................................................................80
第六章 硬體架構設計........................................................................................................81
1 符碼邊界同步硬體架構........................................................................................81
2 取樣時脈偏移補償與硬體架構............................................................................82
3 FFT硬體架構.........................................................................................................88
4 改良型MGC頻域等化器硬體架構.......................................................................97
第七章 晶片實現..............................................................................................................107
1 晶片設計流程......................................................................................................107
2 定點數分析..........................................................................................................108
3. FPGA驗證...........................................................................................................112
4 晶片設計結果......................................................................................................114
4.1 模擬結果驗證......................................................................................114
4.2 晶片結論..............................................................................................116
5 硬體比較..............................................................................................................118
第八章 結論與未來展望..................................................................................................119
參考文獻............................................................................................................................121
 

                                

[1] 蒲冠志, 電力線通訊(PLC)系統工程系列專刊 (三) ,2007
http://www.communications.org.tw/communications/upfiles/%E9%9B%BB%E5%8A%9B%E7%B7%9A%E9%80%9A%E8%A8%8A(PLC)%E7%B3%BB%E7%B5%B1%E5%B7%A5%E7%A8%8B%E7%B3%BB%E5%88%97%E5%B0%88%E5%88%8A(%E4%B8%89)%EF%BC%9A%E9%9B%BB%E5%8A%9B%E7%B7%9A%E9%80%9A%E8%A8%8A%E7%B3%BB%E7%B5%B1.pdf
[2] Andrea M. Tonello,Power Line Communications:Advances in Channel Modeling and Filter Bank Modulation,2010
http://www.strath.ac.uk/media/departments/eee/cesip/Prof_Tonello_-_Power_Line_Com munications.pdf
[3] D. Matiæ, “OFDM as a possible modulation technique for multimedia applications in the range of mm waves,” TUD-TVS, Oct. 1998
[4] A.Peled and A. Ruiz, “Frequency domain data transmission using reduced computational complexity algorithms,” in Proc. IEEE International Conference on ICASSP, vol. 5, April, 1980, pp. 964-967.
[5] IEEE Standard for Broadband over Power Line Networks: Medium Access Control and Physical Layer Specifications,IEEE,2010
[6] C. Hsiao, C. Y. Chen, T. D. Chiueh, “Design of a dual-mode baseband receiver for 802.11n and 802.16e MIMO OFDM/OFDMA,” VLSI-DAT 2009, pp. 331-33.
[7] Alan V. Oppenheim, Ronald W.schafer, Discrete Time Signal Processing, 3/E., Prentice Hall, New Jersey, 2009
[8] M.Peeters and Alcatel, “Synchronization with DMT Modulation”, IEEE Communications Magazine, vol. 37, April 1999.
[9] M. Speth, S. A. Fechtel, G. Fock, and H. Meyr, “Optimum Receiver Design for Wireless
Broad-Band Systems Using OFDM - Part I,” IEEE Transactions on Communications,
vol. 47, no. 11, November 1999.
[10] S. Haykin, Adaptive Filter Theory, fourth ed., Prentice Hall, New Jersey, 2002
[11] M. T. Shiue and S. S. Long, “A Blind Frequency-Domain Equalization Algorithm for
OFDM/DMT Systems Based on AGC and Carrier Recovery”, ITC-CSCC, July 2005.
[12] C. F. Wu, M. T. Shiue and C. K. Wang, “Joint Carrier Synchronization and Equalization
for Packet-Based OFDM Systems in Multipath Fading Channel”, IEEE Transactions on
Vehicular Technology. April 2009. pp1-5.
[13] R. E. Best, Phase-Locked Loops, third ed., McGraw-Hill, 1997
[14] J-J. van de Beek, O. Edfors, M. Sandell, ”On Channel Estimation in OFDM Systems”, IEEE, 1995
[15] Floyd M. Gardner, “Interpolation in Digital Modems – Part II : Implementation and Performance”, IEEE Transactions on communications VOL. 41, NO. 6, June 1993.
[16] M. Hsieh, C.Wei, “Channel estimation for OFDM systems based on comb-type pilot
arrangement in frequency selective fading channels,” IEEE Transactions on Consumer
Electron., vol. 44, no. 1, Feb. 1998
[17] 張朝凱,“用於正交分頻多工通信系統之快速傅立葉轉換處理器之研究設計”,交通大學 ,電子工程系碩士論文 ,2002.
[18] S. Coleri, M. Ergen, A. Puri and A. Bahai, ”Channel Estimation Techniques Based on Pilot Arrangement in OFDM Systems”, IEEE Trans. Broadcasting,September 2002
[19] Pei-Yun Tsai, Tzi-Dar Chiueh, “Frequency-Domain Interpolation-Based Channel Estimation in Pilot-Aided OFDM Systems”, IEEE Vehicular Technology Conference, May 2004
[20] K. Itoh. Analysis of the phase unwrapping problem. Applied Optics, 21(14), 1982.
[21] A.Maiga,J-Y.Baudais,and J-F. Helard, “Very High Bit Rate Power Line ’Communications For Home Networks,” IEEE ISPLC09, April 2009,Dresden, Germany.
[22] E. Guerrini, G. Dell’Amico, P. Bisaglia, L. Guerrieri, “Bit-loading algorithms and SNR estimate for HomePlug AV” IEEE ISPLC ’07,pp.419-424, 26-28 March 2007
[23] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Transactions on Electronic Computers, vol. EC-8, no. 3, September 1959
[24] R. Andraka “A survey of CORDIC algorithms for FPGA based computers,” International Symposium on Field Programmable Gate Arrays, 1998
[25] Y. H. Hu, “The Quantization Effects of the CORDIC Algorithm,” IEEE Transactions on Signal Processing, vol. 40, no. 4, April 1992
[26] 陳右昀,“應用於PLC系統之AGC-CR通道等化技術”,中央大學 ,電機工程學系碩士論文 ,2008.
[27] H.-J. Kim and B.-G. Nam, “A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System” In IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
[28] T.A. Brubaker and J.C. Becker, “Multiplication Using Logarithms Implemented with Read-Only-Memory,” IEEE Trans. Computers,pp. 761-766, 1975.
[29] Mitchell, John N., “Computer Multiplication and Division Using Binary Logarithms” in TEC. 1962., Aug. 1962.
[30] Combet, M., “Computation of the Base Two Logarithm of Binary Numbers” in PGEC. 1965., Dec. 1965.
[31] SanGregory, S.L., “ fast, low-power logarithm approximation with CMOS VLSI implementation” in MWSCAS. 1999., Aug 1999.
[32] Abed, K.H. , “CMOS VLSI implementation of a low-power logarithmic converter” in TC. 2003., Nov. 2003.
[33] Hall E.L., Lynch D.D., Dwyer S.J., “Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications” in T-C. 1970., Feb. 1970.
[34] Byeong-Gyu Nam, “A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems” in ESSCIRC.2007., Munich, European, Sept. 2007.
[35] Neil H.E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI Design: A Systems Prespective,”Addison Wesley,1994.
[36] M. Zimmermann, K. Dostert, “A Multipath Model for the Powerline Channel”, IEEE
Transactions on Communications, vol. 50, no. 4, Apr. 2002
[37] W.-C.Yeh and C.-W. Jen, “High-speed and low-power split-radix FFT,”IEEE Transactions on Acoustics, Speech, and Signal Processing, Volume.51 Issue.3, pp. 864-874, Mar 2003.
[38] Y. Chen, Y.-W. Lin, and C.-Y. Lee, “A block scaling FFT/IFFT processor for Wimax applications,” in Proc. 2nd IEEE Asian Solid-State Circuits Conf., Hangzhou, China, pp. 203–206, Nov. 2006.
[39] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A dynamic scaling FFT processor for DVB-T applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2005–2013, Nov. 2004.
[40] L. G. Johnson, “Conflict free memory addressing for dedicated FFThardware,” IEEE Trans. Circuits Syst. II., Analog Digit. Signal Process.,vol. 39, no. 5, pp. 312–316, May 1992.

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