此論文裡我們提出了一套利用Verilog及Verilog-A硬體描述語言，來建立二階三角積分數位類比轉換器的理想行為模型，此目的是為了提升模擬層級，縮短電路的模擬時間，使數位電路與類比電路可提早在行為層級作整合，加速整個電路的設計流程。
為了使我們電路的行為模型更接近實際傳統的電晶體層級的模擬結果，我們將三角積分數位類比轉換器中交換電容積分器電路的非理想效應加以考慮。在非理想效應中，我們考慮了積分器增益(DC-Gain)、積分器外部轉換速率(External Slew Rate)、積分器穩態響應(Settling Time)。接下來我們利用由下而上(Bottom-up)的驗證方法，並建立了一套標準參數萃取流程，將實際電路的非理想因素萃取出來，再將萃取出來的非理想效應參數加入到我們所建立的行為模型裡，使我們建立的三角積分數位類比轉換器的行為模組更接近實際電路的行為，並達到快速模擬的目的。

In this thesis, we use hardware description language Verilog and Verilog-A to build the second-order sigma-delta digital to analog converter. Our goal is reduced the simulation time of circuit, the simulation model needed to promote the higher abstract level. We can early integrate the digital and analog circuit in the behavioral model to speed up the design procedure.
In order to let our circuit behavior model close to the simulation result of traditional real transistor level, we consider the non-ideal effect of switch capacitance integrator in the sigma-delta digital to analog converter. For the non-ideal effects, we consider the DC-Gain, External Slew Rate and Settling Time of the integrator. Then we use the Bottom-up verifiable method to build up a standard parameter extracted procedure. We first extract the non-ideal factors form real circuits, and then put the extracted non-ideal effect parameters to the behavior model which is built for simulation. This procedure will help the simulation result to be near to the truth and reach to the goal of high-speed simulation.

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