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研究生： 徐仁乾
Jen-Chien Hsu
論文名稱： 使用低增益寬頻率調整範圍壓控震盪器
A 1.25-GHz, 8-phase phase-locked loop with low gain and wide tuning range VCO
指導教授： 蘇朝琴
Chau-Chin Su
劉建男
Chien-Nan Liu
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 91
語文別： 英文
論文頁數： 70
中文關鍵詞： 雙迴路 、鎖相迴路 、時脈抖動
外文關鍵詞： PLL, Dual Loop, Jitter
相關次數： 點閱：16  下載：0 
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    • 在這一個論文中，我們設計了兩個鎖相迴路，第一個是使用傳統電荷充放器(Charge pump)以及相位頻率偵測器(Phase frequency detector)為基本架構的鎖相迴路，操作在1.25GHz並有多相位的輸出。第二個鎖相迴路使用雙迴路架構，並使用兩個控制訊號來控制一個粗調/微調壓控震盪器，這個雙迴路的架構可以降低控制電壓雜訊所造成的時脈抖動，當雙迴路鎖相迴路在獲取狀態時，兩個迴路同時工作以達成鎖定，當鎖相迴路達到穩定時，粗調部分的迴路將會停止工作並且讓微調部分的迴路維持鎖定狀態，因為微調部分的迴路具有較小的壓控震盪器(Voltage controlled oscillator)增益，所以由控制電壓雜訊所產生的時脈抖動將會縮小。兩個鎖相迴路都可以應用在高速傳輸介面(High speed serial link)的傳送端。由模擬的結果得到第一個鎖相迴路具有6ps的時脈抖動，而第二個鎖相迴路具有3.8ps的時脈抖動。兩個鎖相迴路都可以使用台機電0.18 1P6M製程以及操作在1.8伏特。

    In this thesis we design two phase-locked loops. The first phase-locked loop is a traditional one which utilize charge-pump and phase-frequency detector as the basic structure. It operates at 1.25GHz with multi-phase outputs. The second phase-locked loop is a dual loop phase-locked loop using the coarse/fine tune voltage controlled oscillator and two control paths. The dual loop structure can suppress the jitter induced by the control voltage noise. When the dual loop phase-locked loop is in acquisition state, both loops are active to achieve lock. After the phase-locked loop is in the steady state, the coarse tune loop stops working and leaves the fine tune loop to maintain the lock. Because the fine tune loop has the control path with smaller VCO gain, the jitter induced by the control voltage noise will be suppressed. Both phase-locked loops can be applied in the high speed serial link transmitter. The simulation results shows that the first phase-locked loop has 6ps peak to peak jitter and the second has 3.8ps peak to peak jitter. Both phase-locked loops can be fabricated in TSMC 0.18μm 1P4M technology with 1.8V power supply voltage.

    Abstract i Table of contents ii List of Tables iv List of Figures v Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Introduction 3 1.3 Thesis organization 3 Chapter 2 Background Study 5 2.1 Types of noise 5 2.2 Device noise analysis 8 2.3 Types of noise sources in PLL and the transfer functions 11 2.4 Methods of reducing clock jitter 12 2.4.1 Loop parameter optimization 13 2.4.2 Model improvement 13 2.4.3 System structure of phase-locked loop improvement 13 Chapter 3 1.25-GHz, 8-phase PLL design 15 3.1 Phase-locked loop design 15 3.1.1 System architecture 15 3.1.2 Phase frequency detector design 16 3.1.3 Charge pump design 19 3.1.4 Voltage controlled oscillator design 22 3.1.5 Divider design 30 3.1.6 The integration of PLL 33 3.2 Simulation result 34 3.2.1 Phase frequency detector simulation result 34 3.2.2 Charge pump simulation result 35 3.2.3 Voltage controlled oscillator simulation result 36 3.2.4 Divider simulation result 37 3.2.5 Phase-locked loop simulation result 37 3.3 Layout and testing consideration 38 Chapter 4 PLL with low gain and wide tuning range VCO 42 4.1 Motivation 42 4.2 System architecture 43 4.3 Coarse/fine tune voltage controlled oscillator 43 4.4 FSM design 45 4.5 UP/DOWN counter design 48 4.6 DAC design 48 4.7 Reset circuit design 51 4.8 Simulation result 52 4.9 Discussion 56 Chapter 5 Conclusion 57 Bibliography 58

    [1]Ali Hajimiri, Thomas H.Lee, “A general theory of phase noise in electrical oscillators” IEEE journal of solid-state circuits, vol. 33. no. 2, February 1998.
    [2]John A. McNeill, “Jitter in ring oscillators” IEEE journal of solid-state circuits, vol.32, no. 6, June 1997.
    [3]Behzad Razavi, “Design of analog CMOS integrated circuits” McGraw-Hill international edition.
    [4] Marc de Jong, “Sub-Poissonian shot noise” Published in Physics World, August 1996, page 22
    [5]I. A. Young, J. K. Greason, J. E. Smith, and K. L. Wong, “A PLL clock generator with 5 to 110MHz lock range for microprocessors,” ISSCC Dig. Tech. Papers, Feb. 1992, pp.50-51.
    [6]H. Ransijn and P. O’Connor, “A PLL-based 2.5Gb/s GaAs clock and data regenerator IC,” IEEE J. Solid-state Circuits, vol. 26, pp. 1345-1353, Oct. 1991.
    [7]J. A. McNeill, “Jitter in ring oscillators,” Ph.D. dissertation, Boston University, 1994.
    [8]Mozhgan Mansuri, Chih-Kong Ken Yang, “Jitter optimization based on phase-locked loop design parameters ”ISSCC 2002/session 8/high speed timing/8.1
    [9]Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino, “Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1:8 demux”IEEE journal of solid-state circuits, vol. 37, no. 1, January 2002.
    [10]Wilbur B. Davenport, William L. Root, “An introduction to the theory of random signals and noise” New York/McGraw-Hill/c1958
    [11]William B. Wilson, Un-Ku Moon, Dadaba R. Lakshmikumar, Liang Dai, “A CMOS self-calibrating frequency synthesizer”
    [12]John G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques” IEEE journal of solid-state circuits, vol. 31, no. 11, November 1996.
    [13]Won-Hyo Lee, Jun_dong Cho “A high speed and low power phase-frequency detector and charge-pump” IEEE 1999.
    [14]Kuo-hsung cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang, “A difference detector PFD for low jitter PLL”IEEE 2001.
    [15]Sadeka Ali, Faquir Jain, “A Low jitter 5.3GHz 0.18-um CMOS PLL based frequency synthesizer” IEEE radio frequency integrated circuits symposium.
    [16] Chang, R.C, Lung-Chih Kuo, “A new low-voltage charge pump circuit for PLL” Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 5, 2000
    Page(s): 701 -704 vol.5.
    [17]Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi,Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Hazuyuki Nakamura, Masakazu Yamashina, “A 0.1um CMOS, 1.2v, 2GHz Phase-locked loop with gain compensation VCO” IEEE 2001 custom integrated circuits conference.
    [18]frank herzel, Behzad Razavi, “A study of Oscillator jitter due to supply and substrate noise” IEEE transations on circuits and systems-2:analog and digital signal processing. Vol. 46, no. 1, January 1999.
    [19] Djahanshahi, H., Salama, C.A.T., “Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications” Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 6 , Jun 2000 Page(s): 847 -855.
    [20]Woogeun Rhee “Design of low-jitter 1-GHz phase-locked loops for digital clock generation” IEEE 1999.
    [21]Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu, “A fast locking and low jitter delay-locked loop using DHDL”IEEE journal of Solid-state circuits, vo. 38, NO. 2, February 2003.
    [22]Heng-Chih Lin “Analog Design Challenges in nanometer CMOS technologies (130nm 90nm,and beyond)”Deep submicron Mixed-signal integrated circuits design workshop.
    [23]P.H. Lu, “Layout techniques for mixed-signal IC”, CIC training Manual.
    [24]B.S. Yu, “High speed serial link for inter-chip communication”, MS. dissertation, National Central University, 1994.
    [25]J. Yuan and C. Svensson, “High speed CMOS circuit technique,” IEEE Journal of Solid-state circuits, vol. 24, pp 62-70, 1989.
    [26]Maxida, “Multi-module synchronization methodology.” Master Degree dessertation of National Central University 2002.
    [27]Best, “Phase-locked loops, third edition” McGRAW-HILL INTERNATIONAL.
    [28]Neil H. E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI design, second edition” Addison Wesley.
    [29]Seema Butala Anand, Behzad Razavi, “A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology” IEEE 2000 custom integrated circuits conference.
    [30]Nelson Nagle, Carroll Irwin, “Digital logic circuit analysis & design” Prentice Hall.
    [31]Johns, “Analog integrated circuit design”Wiley.

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