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研究生： 游爵豪
Jue-Hao You
論文名稱： 適用於OC-192收發機之頻率合成器和時脈與資料回復電路
Clock Multiplier Unit and Data/Clock Recovery for OC-192 Transceiver
指導教授： 劉建男
Chien-Nan Liu
陳巍仁
Wei-Zen Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 91
語文別： 英文
論文頁數： 125
中文關鍵詞： 時脈與資料回復電路 、頻率合成器
外文關鍵詞： CDR, transceiver, CMU, OC-192
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    • 目前光纖網路應用在高速和長程傳輸通訊已經變成一個主要的趨勢。今日，高速率光纖傳輸標準主要是依循SONET標準。骨幹網路中OC-192 SONET的傳輸速率接近10Gbps，該速率可望很快在骨幹網路中普及並應用在終端網路之中。同時隨著高速光纖傳輸網的推廣，每個關鍵元件的價格與功率開始受到關注，高頻寬光通訊網路的一個關鍵元件是收發機。我們的目的便在於開發適用於SONET OC-192收發器之時脈產生電路和時脈與資料回復電路。在傳送端，經過編碼的資料信號需經由多工器將低速之並列信號轉成一高速串列信號，因此需一時脈產生電路產生所需之高速時脈信號對信號源取樣。在接收端，資料與時脈回復電路必須擷取NRZ信號之頻率與相位，並據此產生精準之時脈信號以對輸入信號進行取樣，以降低接收信號之錯誤產生率。
    時脈產生電路之主要實現方式為鎖相迴路式之頻率合成器，主要目的在提供多工器一個資料取樣之參考信號源，其功能依據SONET OC-192所確立之標準，由一622.08MHz本地振盪源經頻率合成達到一9.9533GHz之輸出參考信號。同時為達到廣泛之應用，壓控振盪器之輸出頻段將包含在10Gb/s附近之各種通訊標準。此電路採用TSMC 0.35μm SiGe BiCMOS製程技術，操作電壓為3.3V。其中一個單獨之10GHz除頻器已經由設計並驗證可操作頻段為500MHz ~ 9.1GHz，晶片面積約1毫米×0.8毫米，同時消耗功率78.7毫瓦。此除頻器將可應用於產生降頻之時脈信號，以作為序列至並列信號轉換與解多工器之用，或應用於10GHz之頻率合成器。本論文所提出之頻率合成器為全差動式，具有改善相位雜訊與排除電源雜訊之優點。其晶片面積約2毫米×1毫米，同時消耗功率230.4毫瓦。
    鎖相迴路式資料回復電路兼具高頻操作與易於積體電路化之優點，同時可藉由相頻偵測器之自我修正達成時脈與資料之自行校準到位，因此傳統上高頻之資料與時脈回復電路多採鎖相迴路式架構。本論文實現一個無須參考信號之鎖相迴路式高速時脈與資料回復電路。本電路使用二位元式相位比較器，因此傳統鎖相迴路線性模型將不適於此。一個適用於二位元式資料與時脈回復電路之線性模型在本論文中提出，藉此設計一個符合SONET OC-192所規定雜訊抖動標準之資料與時脈回復電路。此電路亦採用TSMC 0.35μm SiGe BiCMOS製程技術，操作電壓為3.3V。其架構為全差動式，同時輸出頻段也將包含在10Gb/s附近之各種通訊標準。系統之迴路頻寬為4.18MHz、抖動峰值為0dB、抖動產生的峰對峰值約為5ps，達到OC-192所規定雜訊抖動標準，整體晶片消耗功率約589.1毫瓦。

    The optical network applies in the high-speed and long-haul communications has become a major trend presently. Today, the highest speed for wired data communication is reached using optical fiber transmission operating in accordance with the SONET (Synchronous Optical Networking Standards) standards. The data rate of the SONET OC-192 is close to 10Gb/s and it expects that the data rate of 10Gb/s will be universal in backbone network and applied in terminal networks. And the transceiver is the critical device in high-speed optical networks. The goal in the thesis is to develop a clock multiplier unit and clock/data recovery circuit that suit to the SNOCT OC-192 transceiver. At the transmitter end, the encoded parallel data must be transformed into serial signals by MUX and therefore a CMU is needed to generate a high-speed reference signal for parallel-to-serial data conversion and multiplexing. At the receiver end, a CDR circuit derives the input frequency and phase of the NRZ signals and generates a high precision clock to sample the incoming data so as to reduce the bit error rate.
    Clock multiplier Unit is accomplished by using PLL-based frequency synthesizer. The main goal is to generate a reference signal for multiplexer. Its function is to synthesize a 9.9533GHz output signal form a 622.08MHz reference source according to the SONET OC-192 standard. For various applications, the output frequency range of the oscillator covers that of various communication standards around 10Gb/s. The CMU circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. An individual chip of 16:1 static frequency divider has been designed and demonstrated. Its operation range is 500 MHz ~ 9.1 GHz, chip size is 1 × 0.8 mm2, and power consumption is 78.7mW. It can be used to generate down-frequency clock signals for demultiplexer and used in frequency synthesizer. A fully differential clock multiplier unit presented in the thesis achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture. The CMU has a die size of 2.1 × 1.1 mm2 and consumes 230.4mW from 3.3 V.
    PLL-based CDRs are benefited from capabilities of high frequency operation and feasibility for monolithic integration. Moreover, the phase frequency detector can adjust the transition edge of the sampling clock and align to that of the input data. Therefore, conventionally, high frequency clock and data recovery circuits are of PLL based type. A PLL-based high-speed CDR circuit without reference signals is achieved in this thesis. Because the phase detector used in the CDR is binary type, the conventional linear model of the PLL does not fit it. A novel analytical linear model for the binary type CDR circuit is addressed. Then a CDR circuit that conforms to the SONET OC-192 jitter requirements is designed by it. The CDR circuit is fabricated in TSMC 0.35μm BiCMOS process and its operation voltage is 3.3V. The architecture of it is fully differential and the output frequency range covers that of various communication standards around 10Gb/s. Finally, the jitter bandwidth is 4.18MHz, jitter peaking is 0dB, and the jitter generation is about 5ps. The jitter performances of it suit the OC-192 jitter requirements and its power consumption is 589.1mW.

    Content Abstract i Content iii List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Research Goals 3 1.3 Thesis Organization 5 1.4 References 6 Chapter 2 Frequency Synthesizer and Clock/Data Recovery in Optical Fiber Systems 8 2.1 Introduction 8 2.2 Transmitter and Receiver Architecture 9 2.2.1 Transmitter 9 2.2.2 Receiver 10 2.3 Frequency Synthesizer 12 2.3.1 Role of Frequency Synthesizer 12 2.3.2 Phase Noise 13 2.3.3 Spurious Tones 14 2.4 Clock and Data Recovery 14 2.4.1 Role of Clock and Data Recovery 15 2.4.2 PLL-Based CDR Circuit 16 2.4.3 Over-sampling-Based Data Recovery 17 2.4.4 Summary 18 2.5 Summary 19 2.6 Reference 19 Chapter 3 A 10GHz Fully-Differential Frequency Synthesizer 21 3.1 Introduction 21 3.2 Phase Looked Loop Fundamentals 22 3.2.1 Phase Locked Loop Fundamental 22 3.2.2 Frequency Synthesizer Architecture 23 3.3 PLL Linear Model 24 3.4 Voltage-Controlled Voltage 26 3.4.1 The principle of the LC-tank VCO 27 3.4.2 Inductor 28 3.4.3 Switching Tuning Mechanism 29 3.4.4 VCO Topology and Simulation Results 30 3.5 16:1 Frequency Divider 32 3.5.1 Two Types of the Digital Frequency Divider 32 3.5.2 Design Method for Low Power Consumption 33 3.5.3 Circuit Implementation 36 3.5.4 Summary 40 3.6 Other Circuitry Design 41 3.6.1 Phase/Frequency Detector 41 3.6.2 Charge Pump 43 3.6.3 Loop Filter 44 3.6.4 Output Buffer 46 3.6.5 Bias Circuit 46 3.7 Simulation and Experimental Results 48 3.7.1 Chip Overview 48 3.7.2 Simulation 49 3.7.3 Layout 51 3.7.4 Measurement Results 53 3.8 Summary 56 3.9 References 57 Chapter 4 Jitter Analysis for PLL-Based CDR Circuit 60 4.1 Introduction 60 4.2 The Reasons for Jitter Production 61 4.2.1 Noise 61 4.2.2 Data Randomness 61 4.2.3 Pattern-Dependant Jitter 62 4.3 The Basic Jitter Requirement for SONET OC-192 62 4.3.1 Jitter Generation 63 4.3.2 Jitter Transfer 63 4.3.3 Jitter Tolerance 64 4.4 Jitter Analysis in Linear PLL-Based CDR 65 4.4.1 Jitter Transfer Analysis 65 4.4.2 Jitter Tolerance Theory and Analysis 67 4.4.3 Jitter Generation 76 4.5 Summary 76 4.6 Reference 76 Chapter 5 A 10Gb/s Clock and Data Recovery Circuit Without Frequency Acquisition 78 5.1 Introduction 78 5.2 Clock and Data Recovery Fundamentals 79 5.2.1 The work of CDR in Receivers 79 5.2.2 NRZ Data Input 80 5.2.3 Phase-Locking CDR Architecture 81 5.3 The CDR Architecture without Reference Clock 83 5.4 Jitter Analysis for Binary CDR Loop 84 5.5 Phase and Frequency Detector 88 5.5.1 Phase/Frequency Detector Architecture 88 5.5.2 The operation 89 5.5.3 Circuit Design 91 5.5.4 Simulation 93 5.6 Other Circuitry Design 94 5.6.1 Charge Pump and Loop Filter 94 5.6.2 Quadrature-Phase VCO 96 5.6.3 Input Buffer 100 5.6.4 Output Buffer 100 5.6.5 Decision Circuit and Bias Circuit 101 5.7 Simulation Results 102 5.7.1 Chip Overview 102 5.7.2 Simulation 104 5.8 Summary 106 5.9 References 107 Chapter6 Conclusion 109 6.1 Conclusion 109

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