本論文中，我們從設計到製作，研究深次微米Si/SiGe異質結構互補型電晶體元件在高頻與低功率消耗電路上的應用。在矽鍺應用於元件結構的設計上，我們利用二維解析軟體MEDICI 做以下幾個研究方向的結構模擬：首先，將矽鍺應用於MOS通道上，在relaxed Si1-yGey 材料上成長一strained Si1-xGex 層來當作p型電洞通道與一strained Si 層來當作n型電子通道，利用其高載子遷移率可以達到高速的要求；其次，分析矽鍺材料使用於源極與汲極之Si1-zGez S/D MOS結構，藉由異質接面能帶偏移而得以改善元件短通道效應降低功率消耗；最後發展一整合的互補型金氧半電晶體結構，使同時具有高速且低功率消耗的優點。我們除了模擬分析所設計結構的電性外，亦將探討模擬時各種機制對電性分析的影響。
我們實際製作矽鍺通道結構的p型矽/矽鍺異質結構電晶體並比較其通道鍺含量的影響，利用UHVCVD沈積三種濃度的矽鍺（鍺摻雜15％、30％、grading）當作電洞通道，並為了降低製程熱預算，避免矽鍺層應力變化，採用低壓化學氣相沉積法沉積TEOS閘極氧化層。最後利用電流-電壓等各式量測方法，探討元件之電性特性。

The traits of valence band offset and enhanced carrier mobility in SiGe/Si material system have attracted a lot of attention for high-speed device applications. In this study, a two-dimensional bandgap engineering technique was performed to design a high performance 0.1 um SiGe CMOSFET. A SiGe/Si heterostructure is proposed; in which strained SiGe layers are not only designed for p-channel but also included in source/drain to form heterojunction. And strained Si layer on SiGe layer is designed for nMOS. Simulation results showed that enhanced current-drive capability and reduced short channel effects are achievable within the proposed structure, which indicates that Si1-xGex/Si CMOSFET is a great benefit for high-speed and low-power CMOS circuit applications. And our experiment measurement result also shows the SiGe channel pMOS have better drive current and low substrate swing.

[2] D. -X. Xu, G. -D. Shen, M. Willander, W. -X. Ni and G. V. Hansson, "n- Si/p-Sii-xGex/n-Si double-heterojunction bipolar transistors," Appl. Phys. Lett., vol. 52, pp. 2239, 1988.
[3] T. Tatsumi, H. Hirayama, and N. Aizaki, "Si/GeoJSioJ/Si heterojunction bipolar transistor made with Si molecular beam epitaxy," Appl. Phys. Lett, vol. 52, pp. 895, 1988.
[4] G. L. Patton, J. H. Comfort, B. S. Meyerson, E. F. Crabbe, G. J. Scilla, E. de Fresart, J. M. C. Stork, J. Y. -C. Sun, D. L. Harame, and J. N. Burghartz, "75 GHzfT SiGe-base heterojunction bipolar transistors," IEEE Electron Device Lett., EDL-II, pp. 171, 1990.
[5] C. Smith and A. D. Welbourn, "Prospects for a heterostructure bipolar transistor using a silicon germanium alloy," in Proc. IEEE 1987 Bipolar Circuits and Technology Meeting, pp. 57-64.
[6] S. S. Rhee, J. S. Park, R. P. G. Karunasiri, Q. Ye, and K. L. Wang, "Resonant tunneling through a Si/ GexSil-x /Si heterostructure on a GeSi buffer layer," Appl. Phys. Lett., vol. 53, pp. 204, 1988.
[7] K. Ismail, B. S. Meyerson, and P. J. Wang, "Electron resonant tunneling in Si/SiGe double barrier diodes," Appl. Phys. Lett., vol. 59, pp. 973, 1991.
[8] T. P. Pearsall, J. C. Bean, R. People, and A. T. Fiory, " GexSil-x, modulation- doped p-channel field-effect transistors," Proc. I stint. Symp. Silicon Molecular Beam Epitaxy, ECS Soft Bound Proc. 85-7, p.366, edited by J. C.Bean (Pennington, NJ, 1985)
[9] H. Dambkes, H. J. Herzog, H. Jorke, H. Kibbel, and E. Kasper, "The n-channel SiGe/Si moduladon-doped filed-effect transistor," IEEE Trans. Electron Devices. ED-33, pp. 633, 1986.
[10] H. Ternkin, T. P. Pearsall, J. C. Bean, R. A. Logan, and S. Luryi, " GexSil-x strained-layer superlattice waveguide photodetectors operating near 1.3 μm," Appl. Phys. Lett, vol. 48, pp. 963, 1986.
[11] H. Ternkin, A. Antreasyan, N. A. Olsson, T. P. Pearsall, and J. C. Bean, "Ge().6Sio.4 rib waveguide avalanche photodetectors for 1.3 μm operation," Appl. Phys. Lett., vol. 49, pp. 809, 1986.
[12] P. J. Wang, B. S. Meyerson, F. F. Fang, J. Nocera, and B. Parker, "High hole mobility in p-type moduladon-doped double heterostructures," Appl. Phys. Lett., vol. 55, pp. 2333, 1989.
[13] R. People, "Indirect band gap of coherently strained GexSil-x bulk alloys on <001> silicon substrates," Phys. Rev., vol. B32, pp. 1405, 1985.
[14] C. G. Van de Walle and R. M. Martin, "Theoretical calculations of heterojunction discontinuities in the Si/Ge system," Phys. Rev., vol. B34, pp. 5621, 1986.
[15] R. People and J. C. Bean, "Band alignments of coherently strained GexSil-x /Si heterostructures on <001> GeySi1-y substrates," Appl. Phys. Lett., vol. 48, pp. 538, 1986.
[16] A. Levitas, "Electrical properties of germanium-silicon alloys," Phys. Rev., vol. 99, pp. 1810, 1955.
[17] M. Glicksman, "Mobility of electrons in germanium-silicon alloys," Phys. Rev, III, pp. 125, 1958.
[18] J. A. Moriarty and S. Krishnamurthy, "Theory of silicon superlattices : Electronic structure and enhanced mobility," J. Appl. Phys. vol. 54, pp. 1892 ,1983.
[19] G. C. Osboum, "Strained-layer superlattices: A brief review," IEEE J. Quantum Electron. QE-22, pp. 1677, 1986.
[20] G. van de Walle and R. Martin, Phys. Rev. B34, pp. 5621, 1986.
[21] Kern Rim, Judy L. Hoyt, and James F. Gibbons, "Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET’s," IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, 2000.
[22] TMA MEDICI vertion 2002, Technology Modeling Associates, Inc., 2000.
[23] G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, “Electron velocity overshoot at room and liquid nitrogen temperatures in Si inversion layers,” IEEE Electron Device Lett., vol. 9, pp. 94-96, 1988.
[24] T. Yamada, J. R. Zhou, H. Miyata, and D. K. Ferry, “In-plane transport properties of Si/SiGe structure and its FET performance by computer simulation,” IEEE Trans. Electron Devices, vol. 41, pp. 1513-1522, 1994.
[25] M. R. Pinto, E. Sangiorgi, and J. Bude, “Silicon MOS transconductance scaling in the overshoot regime,” IEEE Electron Device Lett., vol. 14, pp. 375-378, 1993.
[26] S. K. Chun, and K. L. Wang, IEEE Electron Devices, vol. 39, pp. 2153, 1992.
[27] T. Manku, J. M. McGregor, A. Nathan, and D. J. Roulston, IEEE Trans. Electron Devices, vol. 40, pp. 1990, 1993.
[28] Li PW, Yang YF, Yang ES, Chu J, Meyerson BS. “SiGe pMOSFETs with gate oxide fabricated by microwave electron cyclotron resonance plasma.” IEEE Electron Device Lett., vol. 45, pp. 402, 1994.
[29] S. S. iyer, P. M. Solomon, V. P. Kesan, A. A. Bright, J. L. Freeouf, T. N. Nguyen, and A. C. Warren,”A gate-quality dielectric system for SiGe metal-oxide-semiconductor devices,” IEEE Electron Device Lett.,vol. 12, pp. 246, 1991.
[30] H. Hu, L. T. Su, Y. Yang, D. A. Antoniadis, and H. Smith, “Channel and source/drain engineering in high performance sub-0.1 μm nMOSFET’s using x-ray lithography,” in Symp. VLSI Tech. Dig., 1994, pp. 17-18.
[31] H. Hu, J. Jacobs, L. Su, and D. Antoniadis, “A study of deep-submicron MOSFET scaling based on experiment and simulation,” IEEE Trans. Electron Devices, to ba pulished.
[32] G. W Taylor, “Subthreshold conduction in MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-25, pp. 337, 1978.
[33] R. R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 383, 1979.
[34] YAN. R. H., OURMAZD, A., and LEE, K. F.,”From bulk to SOI to bulk”, IEEE Trans. ED-39, pp. 1704-1710, 1992.
[35] K. lsmail, S. F. Nelson, J. O. Chu, and B. S. Meyerson, Appl. Phys. Lett., Vol. 63, pp. 660, 1993.
[36] K. Ismail, J. O. Chu, and B. S. Meyerson, Appl. Phys. Lett., vol. 64, pp. 3124, 1994.
[37] G. F. Niu and G. Ruan, IEEE Trans. Electron Devices, vol. 42, pp. 2242, 1995.
[38] M. Yoshimi, M. Terauchi, A. Murakoshi, N. Shigyo, and Y. Ushiku, “Technology trends of silicon-on-insulator-Its advantages and problems to be solved’” in IEDM Tech. Dig., pp. 429, 1994.
[39] A. Nishiyama, O. Arisumi, and M. Yoshimi, “Suppression of the floating-body effect in partially-depleted SOI MOSFET’s with SiGe source structure and its mechanism,” IEEE Trans. Electron Devices, vol. 44, pp. 2187, 1997.
[40] “Electrical measurement of the bandgap of N+ and P+ SiGe formed by Ge ion implantation,” in Mater. Res. Symp. Proc., vol. 500, pp. 69, 1994.
[41] M. Ishii, K. Goto, M. Sakuraba, T. Matsura, and M. Kiyanagi, “0.1μm MOSFET with super self-aligned shallow junction electrodes,” in Abstr. 1997 Electrochemical Soc. Spring Meeting, pp. 792.
[42] M. C. Ozturk, N. Pesovic, and S. Gannavaram, “Ultra-shallow Source/Drain Junction for nanoscale CMOS using selective Silicon-Germanium Technology”, Extended Abstracts of international Workshop on junction Technology 2001.
[43] Y. V. Ponomarev et al, IEDM Tech. Digest, pp. 829, 1997.
[44] V. Z-Q. Li et al, IEDM Tech. Digest, pp. 833, 1997.
[45] V. E. Houtsma et al, IEEE Electron Device Lett., EDL-20, pp. 314, 1999.
[46] B. J. Gordon, “C-V plotting:Myths and Methods,” Solid State Technology, pp. 57, 1993.
[47] D. K. Nayak, Kamjo, J. S. Park, J. C. S. Woo, and K. L. Wang, IEEE. Trans. Electron Devices, vol. WD-39, pp. 56, 1992.
[48] D. C. Paine, C. Caragianis, and A. F. Schwartzman, J. Appl. Phys. vol. 70, pp. 5076, 1991.