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研究生： 葉宗皇
Chung-Huang Yeh
論文名稱： 用於改進測試的時變製造過程的疊代估計
Iterative Estimation of Time-Variant Manufacturing Processes for Test Improvement
指導教授： 陳竹一
Jwu-E Chen
口試委員:
學位類別： 博士
Doctor
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 英文
論文頁數： 101
中文關鍵詞： 測試錯誤 、測試規格 、測試防護帶 、缺陷等級
外文關鍵詞： Test errors, test specification, guardband test, defect level
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    • 這項研究以統計方法為基礎，開發一種IC測試模型（DITM），用來評估IC產品的測試良率和品質。為了清楚地表示製造和測試參數，我們將製造能力（DUT電路特性參數）以常態分佈為基礎，然後依次表達與製造能力和測試能力相關的其他參數的標準化參數。最後，我們使用品質-良率圖來了解可製造性參數與可測試性參數之間的相互作用。由於無法得知IC產品的未來分佈，因此我們使用當前產品的電氣特性和產品製造技術來估算未來的產品分佈趨勢。我們比較了Miao–Dalal，DITM和ITRS預測的未來不同的Yt (Test Yield)值。在這三種不同的估計方法之間，很明顯，由以上模擬結果可以清楚了解，DITM可以準確有效地預測未來測試良率Yt。由於測試技術的開發改進速度相當緩慢，因此對於testing house來說，使用現有測試儀器和適當的測試方法，分類出高品質的優質IC已成為一個更大的挑戰。為了提高產品測試良率與品質，我們提出了幾種重複測試的新方案（多重測試方法，重複測試方法和不平衡測試方法），以獲得具有所需產品品質的最大測試良率，這是通過應用《國際半導體技術路線圖》（ITRS）表中的重複測試方法來完成的。最後，通過將重複測試方法應用於2015年ITRS路線圖中的預估的表格中，可以清楚地看出，與傳統測試方法相比，重複測試確實可以將測試結果提高30％以上或更多。

    This study aims to develop an IC testing model (DITM) based on a statistical simulation method to evaluate the test yield and quality of IC products. In order to express the manufacturing and testing parameters clearly, we will take the manufacturability (DUT circuit characteristic parameters) into a standard normal distribution as the basis, and then successively express the standardized parameters of other parameters relative to manufacturability and testability. Finally, we use the quality-yield plot to demonstrate the interaction between the manufacturability parameters and the testability parameters. Since the future distribution of IC products cannot be known, we use current product electrical characteristics and product manufacturing technology to estimate future product distribution trends. Hence, we compared the different future test yield (Yt) values as predicted by Miao–Dalal Yield, DITM, and by ITRS. Between the three different estimation methods, it is clear that the above-simulated result indicated that DITM could accurately and effectively predict future test yield (Yt). Since developmental improvements for testing technologies has been slow, it has become a greater challenge for a supplier to determine the use of existing instruments and tools to achieve quality products with zero defects. To improve product quality, several new schemes of duplicate tests (Multiple test method, Repeated test method, and Unbalanced test method) have been proposed to obtain a maximum yield with the desired qualities. This has been done by applying the duplicate testing methodologies described in Table of the International Technology Roadmap for Semiconductors (ITRS). Finally, with the application of the Repeat test methodology to the table of the test protocol described in the 2015 ITRS Roadmap, it shows clearly that in comparison with the traditional test methodology, Repeat testing can indeed promote the result of test yield by 30% or more.

    Contents 摘要 ……………………………………………………………...……………… i Abstract ………………………………………………………………...…………… ii Acknowledgmments ………………………………………………………….……...…… iii Contents …………………………………………………………………………...… iv List of Figures ………………………………………………………………………...…… vii List of Tables …………………………………………………………………...………… ix Nomenclature ……………………………………………………...……………………… x Chapter 1: Introduction……………………………………….……………………… 1 1-1 Motivation…………………………………………….…………………… 1 1-2 Research Goal………...…………………………………………………… 3 1-3 Research Methodology…………………………………………….……… 4 1-4 Contributions………………………………………………….…………… 5 1-5 Organization and Main Tasks…………………………………...………… 6 Chapter 2: Related Work 9 2-1 IC Test Concept…………………………………………………………… 9 2-2 Calculating the Manufacturing Yield……………………………………… 9 2-3 Predicting the Manufacturing Progress Variation of Future 13 Chapter 3: Testing Yield Estimation and Guardband Testing 16 3-1 A Test Evaluation Technique for VLSI Using………….………………… 16 3-2 Guardband Testing………………………………………………………… 16 3-3 Testing Yield Estimation……………………………..…………………… 18 3-4 Defect Level DL Estimation………………………….…………………… 20 3-5 Guardband test impacts on Yt and Qt……………………………...……… 23 3-6 The Effect of ATE Accuracy on the IC Test Yield and Product Quality…. 25 3-7 Sacrifice Some Test Yield for High Quality……..……………………..…. 27 Chapter 4: Quality–Yield Plot and Forecasting DUT Yield……...………………… 29 4-1 Standardization of manufacturing capability and test capability parameters………………………………………………………...…..…… 29 4-2 Quality–Yield Plot……………………………….……………...………… 31 4-3 Forecasting DUT Yield……………………………….…………………… 33 Chapter 5: A New Scheme of IC Testing………………………….………………… 35 5-1 Testers Lacking up to Date Testing Abilities…………...………………… 35 5-1-1 Use a VLSI tester with an annual improvement of 12% to test manufacturing technology that has an annual improvement of 4%........................................................................................…..……...…… 35 5-1-2 Use a VLSI tester with an annual improvement of 5% to test manufacturing technology that has an annual improvement of 4%........................................................................................…..……...…… 37 5-1-3 Use a VLSI tester with an annual improvement of 3% to test manufacturing technology that has an annual improvement of 4%........................................................................................…..……...…… 38 5-2 A New Scheme of Testing………………………………………………… 39 5-2-1 The First Method: Multiple Testing Scheme………………………..…… 41 5-2-2 High-Quality Goal……..………………….……………………….……… 43 5-2-3 Mltiple -Tests Applying to the ITRS Table for Guardbanding……….…… 45 5-3 The Second Method: A New Unbalanced Testing Scheme……………..… 47 5-3-1 Estimation of Unbalanced Testing………………………………………… 49 5-3-2 Unbalanced-Tests That Apply to Accuracy Requirement Data (300ppm) 51 5-3-3 Unbalanced-Tests That Apply to Accuracy Requirement Data (5ppm)…………………………………………………………...………… 53 5-4 The Third Method: Repeat Testing Scheme………………...…..………… 54 5-4-1 Different Test Methods Affect Test Yield and Test Quality.……..……… 56 5-4-2 By Applying the Repeat Test Methodology to the Table of TEST, ITRS 2015 (300ppm)…………………………………………………………... 58 5-4-3 Maintain 5ppm Quality in VLSI Test Using the Repeat-Test Method....… 60 5-4-4 Decision-Making Methods to Increase Company Profits………………… 62 5-4-5 Maximum Economic Benefits…………………………..………………… 64 Chapter 6: Conclusion……………...………………………………………………… 66 Future Work …………….…………………………………………………..…………… 68 References ……………………………………………………………………...……… 70 Appendix A.Manufacturing Yield Estimation…………………………………...…… 74 B.Testing Yield Estimation...………………………………………...…… 76 C.Defect Level Estimation…………………………………………...…… 78 D.A New Multiple Testing Scheme.………….……………………...…… 80 E.Standardization of Manufacturing and Testing Parameters...……...…… 82 Publication List ………………………………………………………………………… 84 A. Journal Papers……………………………………….………….……… 84 B. Conference Papers…………………………………...….……………… 84 List of Figures Fig. 2-1 A manufacturing and test process with test errors………………….………..……….10 Fig. 2-2 The probability density function (normal one-dimensional distribution)……....……10 Fig. 2-3 A graph of the probability distribution vs chip delay time.. …………...…………….12 Fig. 2-4 Design specification impact on manufacturing yield. ……………………………….13 Fig. 3-1 An example of test specifications for IC testing. …………………………………….16 Fig. 3-2 The plots of probability density of a normal chip delay time. ……………………….17 Fig. 3-3 The traditional guardband test. …………………...………….…………….……..….19 Fig. 3-4 Traditional test . ……………………….………………….…………………..….22 Fig. 3-5 The influence of tester accuracy on test yield and test quality. ………….….……….23 Fig. 3-6 Influence of tester test specifications toward test yield and test quality…….……….25 Fig. 3-7 Test accuracy impact on test yield and test quality…………………………………..26 Fig. 3-8 The influence of tester specifications on test quality at the same defect level. .….….27 Fig. 4-1. Standardization of all evaluations………………………………….………..……….31 Fig. 4-2. Quality–yield plot (manufacturability index Cm = 2) ……………….……..……….31 Fig. 4-3 Quality–yield plot (manufacturability index Cm = ±0.5, ±1, 0, 2, and 3)……………33 Fig. 4-4 Three kinds of models to predict the future test yield (Yt)…………...………………34 Fig. 5-1 Testers lacking up to date testing abilities……….………………..…….……………36 Fig. 5-2 The 12% annual improvement of tester...………….…...……………....….…………36 Fig. 5-3 The 5% annual improvement of tester. …………………….………...………………37 Fig. 5-4 The 3% annual improvement of tester. ………………………………………………38 Fig. 5-5 Different developmental speeds for testing and manufacturing technologies. …..…..40 Fig. 5-6 The decision diagram for Multiple testing ( )…………..…………..……..………42 Fig. 5-7 The decision diagram for Multiple testing ( )…………………….………………42 Fig. 5-8 An example of how the yield is sacrificed to gain high quality products. ( ).……43 Fig. 5-9 Multiple tests for maximizing the yield without degrading quality…….……………45 Fig. 5-10 Comparison of traditional testing method and Multiple testing ……......…46 Fig. 5-11 The proposed decision diagram for Unbalanced Testing ( )………...……..……48 Fig. 5-12 Test methods that impact on Yt and Qt. ………………………….…..…..…………50 Fig. 5-13 The methods used to estimate the test yield in future products (300ppm). ...………53 Fig. 5-14 Applying the Unbalanced testing method to the ITRS Table (5ppm). ………..……54 Fig. 5-15 The decision diagram for Repeat testing ( ).………………………..……………55 Fig. 5-16 An example three test schemes to modifying the test specifications ( )…...……56 Fig. 5-17 An example of tester edge distribution and loss. ………………….………..………57 Fig. 5-18 Testing methods and decision-making affect the yield of testing (300ppm)…….…59 Fig. 5-19 Maintaining the desired 300 ppm DL as a function of time. ……………….………59 Fig. 5-20 Test methods change the test results (maintaining the desired 5 ppm DL)…………61 Fig. 5-21 Increase the yield of the test and maintain the required 5 ppm DL...…….…………61 List of Tables Table 2-1 Different design specification versus different future product manufacturing yield……………………………………………………………………………………………13 Table 2-2 The International Technology Roadmap for Semiconductors 1999 and 2015 table…………………………………………………………………………..……….…….…15 Table 3-1 The value of test guardband impact on test result.…………………………………24 Table 3-2 Tester accuracy impact on Yt and Ym.………………………………………………26 Table 3-3 Tester specifications impact on Yt at the same defect level………………………...28 Table 4-1 Quality–yield plot (manufacturability indexes Cm = ±0.5, ±1, 0, 2, and 3).….……32 Table 4-2 Manufacturing progress parameter (α) affects the change of test yield (Yt)…….…34 Table 5-1 The use of 3, 5, 12% annual improvement of tester to test the 4% annual improvement of semiconductor manufacturing process………………………………….……39 Table 5-2 Multiple tests improvement test yield…………………………….……….……..…44 Table 5-3 Multiple tests for maximizing the yield without degrading quality (300ppm)…..…47 Table 5-4 Test Method impact on Yt & Qt……………………………………………………50 Table 5-5 A comparison of the Yt and DUT from two test methods.…………………………52 Table 5-6 A method used to improve the measurement yield in IC testing...…………………57 Table 5-7 Repeated test method to improve test yield……………………...…………………62

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