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研究生： 林友正
Yo-chen Lin
論文名稱： eHVA-II: 一個具功能模型的類比電路
eHVA-II: An Extended Hierarchical Variance Analyzerwith Functional Model for Analog Circuits
指導教授： 陳竹一
Jwe-E Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 98
語文別： 中文
論文頁數： 45
中文關鍵詞： 階層式變異數
外文關鍵詞： An Extended Hierarchical Variance
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    • 摘要
    隨著現代半導體製程技術進入深次微米時代，製程變動對於電路效能的影響越來越嚴重。因為製程變動已被觀察出存在空間相關性的緣故，我們需要高速且可考慮製程變動相關性的方法使我們可以更準確的估計電路效能參數的變動以減少設計疊代成本。我們提出一個可以計算類比電路各階層參數變異數之高速變異數分析法的延伸架構，使之能探討當製程參數存在相關性的情況，並利用實驗進行比較，實驗的結果顯示此分析器的精確度及效率皆相當出色。

    Abstract
    As technological scales down to ultra-deep-submicron, the impact of process variation on circuit performance gains importance. For it has been observed that the process variations are spatially correlated, analysis with consideration of process parameters correlations and high computational efficiency is needed to help estimating variations of circuit performance accurately and reducing the cost of design iteration. We present an extended scheme of prior high speed hierarchical variance analysis method to calculate the variances of parameters at each hierarchical layer in analog circuits while taking process parameters correlations into account. Experimental results show that the method achieves high computational accuracy.

    目錄 中文摘要 i Abstract ii 誌謝 iii 目錄 vi 圖目錄 vi 表目錄 viii 第一章 緒論 1.1製程變動對先進製程的挑戰 1 1.2統計容限模型 2 1.2.1 蒙地卡羅分析 3 1.2.2 階層式變異數分析法 3 1.3研究動機 3 第二章 階層式變異數分析法 2.1架構系統模型 5 2.2階層式變異數的成分分析 6 2.3階層式變異數分析法統計模型 8 2.4階層式變異數分析法的應用 9 第三章 考慮製程相關性的統計模型(eHVA) 3.1階層式變異數分析法(HVA)的使用前提 11 3.2統計學的定義及定理介紹 11 3.3延伸型階層式變異數分析法統計模型(eHVA) 17 第四章 統計模型的優缺點比較 4.1實驗設定 21 4.1.1蒙地卡羅統計模型 25 4.1.2階層式變異數分析統計模型 26 4.1.3延伸型階層式變異數分析統計模型 28 4.2實驗結果 29 4.2.1精確度的比較 29 4.2.2效率的比較 41 4.2.3複雜度分析 42 4.2.4記憶體使用量 43 第五章 結論…………………………………………………… 44 參考文獻 45

    參考文獻
    [1] F. Liu and S. Ozev, “Hierarchical analysis of process variations for
    mixed-signal systems” in Proc. IEEE ASP-DAC, Jan. 2005, PP.465 – 470
    [2] A. Stuart, and J. K. Ord, Kendall''s advanced theory of statistics, London: Griffin, 5thed, 1987
    [3] F. Liu, J. J. Flomenberg, D. V. Yasaratne, and S. Ozev, “Hierarchical variance analysis for analog circuits based on graph modeling and correlation loop tracing,” in Proc. Design Automation and Test in Europe, PP.126-131
    [4] S. Director, P. Feldmann, and K. Krishna, “Statistical integrated circuit design,” IEEE Journal of Solid-State Circuits, Mar. 1993, PP. 193 – 202
    [5] B. Razavi. Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
    [6] L. J. Bain, and M. Engelhardt, Introduction to Probability and Mathematical Statistics, PWS-KENT Pub, 1992.
    [7] “WIKIPEDIA” http://www.wikipedia.org/
    [8] S. S. Wang, “EMN_RVG: An Enhance Multivariate Normal Random Vector Generator for Circuit Analysis,” master thesis, Dept. Electrical Engineering, Chung-Hua University, Hsinchu, 2001
    [9] G. Gielen, and W. Dehaene, “Analog and digital circuit design in 65 nm CMOS: end of the road?,” in Proc. Design Automation and Test in Europe, 2005, PP. 37 – 42
    [10] D. Frank, "Parameter variations in sub-100nm technology," ISSCC microprocessor workshop, Feb. 2004.
    [11] F. Liu and S. Ozev, “Efficient Simulation of Parametric Faults for Multi-Stage Analog Circuits,” IEEE International Test Conference, Oct. 2007, PP.1 – 9
    [12] F. Liu and S. Ozev, “Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits,” IEEE International Test Conference, Oct. 2005, PP.161-168
    [13] F. Liu, and S. Ozev, “Statistical Test Development for Analog Circuits under High Process Variations,” IEEE Computer-Aided Design of Integrated Circuits and Systems, Aug. 2007, PP.1465–1477
    [14] F. Liu, E. Acar and S. Ozev, “Test Yield Estimation for Analog/RF Circuits over Multiple Correlated Measurement,” IEEE International Test Conference, Oct. 2007, PP.1 – 10

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