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研究生： 郭星辰
Guo Xingchen
論文名稱： 智慧型感測器網絡嵌入式硬體設計和實作
Embedded Hardware Design and Implementation of Smart Sensor Network
指導教授： 陳慶瀚
Pierre Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 資訊工程學系
Department of Computer Science & Information Engineering
論文出版年： 2013
畢業學年度： 101
語文別： 中文
論文頁數： 106
中文關鍵詞： 智慧感測器 、智慧感測器網絡 、硬體化 、Modbus 、嵌入式 、FPGA
外文關鍵詞： Smart Sensor, Smart Sensor Network, Hardware, Modbus, Embedded, FPGA
相關次數： 點閱：17  下載：0 
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    • 現有的智慧感測器系統常缺乏對多感測器的有效管理機制，因此導致處理器負擔大、工作效率低並且耗電量大；而基於處理器的現場總線協議和IEEE1451的智慧感測器開發正面臨即時性、可靠度和硬體成本等多重挑戰。本論文提出一個創新的智慧感測器網路架構，可以有效降低功耗、提高即時效能，並且具有更佳的感測器管理性能。系統包含全硬體化的智慧感測器節點、智慧感測器網路閘道器和基於C++builder的客戶端智慧感測器網路監控程式。
    我們所設計的系統符合智慧感測器定義的非線性校正、自補償、自檢、自診斷，同時進一步滿足智慧感測網路定義的感測器新增拔除、訊號擷取、故障偵測、模式控制、自動配置等功能。系統中以硬體化的Modbus模組為智慧感測器網路通訊基礎，另外採用CRC校驗、ARQ和漢明碼糾錯相配合的機制，以增進即時通訊的可靠度。本研究利用MIAT嵌入式硬體設計方法論進行所有功能模組的嵌入式硬體實作，可提供智慧感測網路的最高性能。此外，系統鮑率、Modbus功能碼和系統模組都可以方便調整並重新配置，兼顧了系統性能和靈活性。最後我們所實現的FPGA雛型系統在使用Altera Cyclone III-C25 FPGA和利用杜邦線短距離通訊的條件下，最高鮑率可達7.06Mbps，網路節點的響應時間為73.8us，網路資料傳輸成功率100%，無資料丟失現象，符合實時性和可靠性的系統需求。

    Existing smart sensor system often lacks effective management mechanisms for multi-sensor system, resulting in a large burden on the processor, low efficiency and high power consumption; while it’s difficult for smart sensor based on processor-based fieldbus protocol and IEEE1451 to achieve the goal of real-time, reliability, low-cost and so on. This paper presents an innovative intelligent sensor network architecture that can effectively reduce power consumption, improve real-time performance, and has a better management performance. This system consists of smart sensor nodes, smart sensor network gateway, both hardware realized , and a client monitoring program base on C++ builder.
    The system we designed meets the definition of smart sensor, such as non-linear calibration, self-compensating, self-inspection and self-diagnosis. What’s more, this system further meets the definition of smart sensor network, like nodes added detection, nodes removal detection, signal acquisition, fault detection, mode control, ID configuration. System uses Modbus hardware modules as the network communication infrastructure. In addition, we adopted the CRC, ARQ and Hamming code error correction mechanism to improve the reliability of real-time communication. In this study, we used Hierarchical Robotic Discrete-Event Modeling for the hardware implementation of all embedded functional modules. Additionally, the baud rate, Modbus functions and hardware modules can be easily adjusted and reconfigured, raising system performance and flexibility. Finally, we implemented FPGA prototype system by using Altera Cyclone III-C25 FPGA and DuPont lines. Under this short-range communication condition, the maximum system baud rate speeds up to 7.06Mbps, the node response time is only 73.8us, and data transfer success rate achieves 100%, with no data losing phenomenon. The system is in line with real time and reliability of system requirements.

    摘 要 II Abstract VII 誌 謝 VIII 目 錄 IX 圖目錄 XIII 表目錄 XVII 第一章、緒論 1 1.1 研究背景 1 1.2 研究目標 3 1.3 論文架構 4 第二章、文獻回顧 5 2.1 智慧感測器 5 2.1.1 智慧感測器類型 5 2.1.2 智慧感測器功能和特點 6 2.1.3 IEEE1451標準 7 2.1.4 智慧感測器實現方案 9 2.2 無線感測器網路 13 2.2.1 無線感測器網路概述 13 2.2.2 無線感測器網路的特點和關鍵技術 14 2.2.3 無線感測器網路的研究動態 16 2.3 現場總線 19 2.3.1 現場總線概述 19 2.3.2 現場總線現狀比較和分析 20 2.3.3 Modbus現場總線協議概述 22 2.3.4 Modbus應用層協議 23 2.3.5 Modbus串列鏈結層實現 26 2.3.6 Modbus 性能評估指標 29 第三章、智慧感測器網路系統設計 33 3.1 總體方案選擇 33 3.2 系統架構圖及分析 34 3.2.1 智慧感測器節點架構 34 3.2.2 智慧感測器閘道器架構 36 3.2.3 客戶端架構 37 3.3 系統功能設計 38 3.3.1 智慧型感測器功能設計 38 3.3.2 智慧網路閘道器功能設計 39 3.3.3 客戶端功能設計 40 第四章、智慧感測網路系統實作 41 4.1 硬體合成方法論 41 4.2 功能輔助模組 43 4.2.1 計時器 43 4.2.2 狀態記錄 43 4.2.3 分頻器 44 4.3 通訊模組 44 4.3.1 Uart模組 44 4.3.2 幀發送模組 47 4.3.3 幀接受模組 48 4.4 感測器管理模組 49 4.5 客戶端通訊模組 51 4.6 智慧感測器節點 52 4.7 智慧感測器閘道器 53 4.8 客戶端軟體 54 第五章、智慧感測器網路系統整合和測試 56 5.1 硬體開發環境 56 FPGA開發平台 56 SIOC 58 感測器周邊 58 5.2 智慧感測器節點效能實驗 59 5.3 智慧感測器網路功能實驗 62 5.3.1 智慧感測器新增驗證 62 5.3.2 智慧感測器編號配置驗證 62 5.3.3 智慧感測器訊號擷取驗證 63 5.3.4 智慧感測網路模式控制驗證 64 5.3.5 智慧感測器故障偵測驗證 64 5.3.6 智慧感測器拔除偵測驗證 65 5.4 智慧感測器網路性能分析 66 5.4.1智慧感測網路性能分析 66 5.4.2智慧感測網路實時性分析 69 5.4.3智慧感測網路可靠性分析 69 第六章、結論 71 6.1 結論 71 6.2 未來展望 72 參考文獻 74 附錄一 78 計時器模組 78 狀態記錄模組 78 分頻器模組 79 附錄二 80 並列串列轉換模組 80 串列並列轉換模組 80 漢明碼編碼模組 81 漢明碼譯碼模組 81 附錄三 82 CRC校驗模組 82 幀發送模組 83 幀接受模組 84 附錄四 85 感測器管理模組 85 I2C_Sart模組 86 I2C_Stop模組 86 I2C_Ack模組 87 I2C_NoAck模組 87 I2C_WaitAck模組 88 I2C_SendByte模組 88 附錄五 89 感測器節點主控模組 89

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