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研究生： 張家祥
Chia-Hsiang Chang
論文名稱： 多模組之相位同步技術
multiple module synchronization methodology
指導教授： 蘇朝琴
Chauchin Su
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 89
語文別： 中文
論文頁數： 48
中文關鍵詞： 多模組相位同步技術 、自動測試機臺 、時序產生器
外文關鍵詞： synchronization methodology, ATE, timing generator
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    • 我們在此提出一多模組相位同步技術。多模組的相位同步是個重要部分對於SOC系統的環境。所提出的同步技術目前是適合應用於整合自動測試機臺。此同步技術的優點是可很容易的增減所需同步模組的個數。同時能提供穩定同步且可調整的時序。而有了此同步且可調整的時序，我們可以用以取代原自動測試機臺的時序產生器。而此同步的機制可以簡化且縮減傳統所需的時序校正所需且冗長的時間。同步機制的模擬是先採用C語言描述加以模擬其機制動作，用以檢視其機制的運作。再來以Verilog硬體描述來模擬硬體實現的環境。模擬的環境設定成接近實際的運作環境。而同步機制所需的相位產生器是以TSMC 1p4m 0.35um 的製程技術設計製作。而其量測的結果可驗證其精細的相位解析度。


    Contents CHAPTER 1INTRODUCTION1 1.1Motivation1 1.2Application in the integration of ATE4 1.3Timing generator5 1.4A dynamic clock synchronization technique7 1.5Point-to-point scheme8 1.6The issues in multi-module synchronization10 1.7Summary11 CHAPTER 2ARCHITECTURE OVERVIEW12 2.1Overview12 2.2Multi-module synchronization mechanism14 2.3Synchronization control logic20 2.4PN address reset finite state machine21 2.5Lead/Lag detection22 2.6PN/data combine24 2.7Data extraction25 2.8Phase compensation decision26 CHAPTER 3THEORETICAL BACKGROUNDS28 3.1Introduction28 3.2Analysis of “lead/lag detection”29 3.3Performance of confidence counter31 CHAPTER 4SIMULATION RESULT AND MEASUREMENT35 4.1Introduction35 4.2The simulation of NRZ clock recovery36 4.3The implementation of NRZ clock recovery37 4.4The measurement of NRZ clock recovery38 4.5Multi-module synchronization simulation result41 CHAPTER 5CONCLUSION47 BIBLIOGRAPHY48

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