摘要
隨著半導體製造技術的進步，最小特徵尺寸持續降低，而且電路密度逐漸增加。在這個同時，增加的時脈速度要求這些電路有更快的訊號轉換速率。如此，在今天的高速電路中，雜訊產生變得愈來愈嚴重。然而，供應電源電壓的減少代表著更低的電晶體臨界電壓。因此，電路的雜訊邊界變得更小。它會造成大量的訊雜比降低，不管是在數位或是混合訊號電路。因此，電路效能將被雜訊所限制。
在這個論文，我們提供一個能察覺雜訊的標準元件庫。有兩個主要的部份在這個目標，雜訊特性化與抑制雜訊元件設計。在雜訊特性化方面，我們介紹特性化交插耦合雜訊的程序與使用CLKINVX1與NAND2X1來當成特性化例子。我們也討論特性化同時轉換雜訊的方法與呈現一些初步的想法。
在雜訊抑制元件設計方面，我們實現了被動抑制電源雜訊元件，去耦合電容，與一個主動抑制電源雜訊模組。它們可以直接抑制在設計者電路中所發生的電源雜訊。模擬結果顯示，主動抑制電源電路能降低負的電源雜訊峰值達33%，降低正的電源雜訊峰值達44%。最後我們將主動抑制電源雜訊電路與晶片上抖動量測電路做結合。這個結合電路可以讓我們直接觀察主動抑制電源雜訊電路所造成的改善。

Abstract
With advances in semiconductor fabrication technology, the minimum feature size continues to decrease and the circuit density increases gradually. At the same time, increasing clock speeds demands these circuits to switch at faster rates. Thus, noise generation becomes more and more serious in today’s high-speed circuits. Moreover, decreasing power supply voltages dictate lower transistor threshold voltage. Therefore, noise margins of circuits become smaller. It causes a significantly signal-to-noise ratio reduction for both digital and mixed-signal/analog circuits. Therefore, the circuit performance will be limited by noise.
In this thesis, we provide a noise-aware standard cell library. There are two major parts in the subject, noise characterization and noise suppression cell design. On noise characterization, we introduce the procedure to characterize the noise behavior and use CLKINVX1 and NAND2X1 as a characterization example. We also discuss the way to characterize simultaneous switching noise and propose some preliminary ideas.
On noise suppression cell design, we implement the passive power supply noise (PSN) suppression cell, decoupling capacitance, and an active PSN suppression module. They can be used to suppress PSN occurring in design’s circuit. The simulation results appeal that the active PSN suppression circuit can have 33% reduction for negative PSN peak and 44% reduction for positive PSN peak. Finally, we combine the active PSN suppression circuit with an on-chip bounce measurement circuit. This combined circuit can let us observe the improvement due to the active PSN suppression circuit directly.

References
[1] W. Roethig, “Library Characterization and Modeling for 130 nm and 90 nm SOC Design,” proceedings of the IEEE International SOC Conference, pp. 383–386, Sep. 2003.
[2] R. Hegde and N. R. Shanbhag, “Towards Achieving Energy-Efficiency in Presence of Deep Submicron Noise,” IEEE Trans. on VLSI Systems, vol. 8, no. 4, pp. 379-391, Aug. 2000.
[3] PrimeTime® SI User Guide, Version W-2004.12, December 2004
[4] Library Complier User Guide: Modeling Timing and Power Technology Libraries, Version W-2004.12, December 2004
[5] A. Kasnavi, J. W. Wang, M. Shahram, and J. Zejda., “Analytical modeling of crosstalk noise waveforms using weibull function,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 7-11 2004, , pp. 141-146
[6] Y. S. Chang, S. K. Gupta, M. A. Breuer, “Analysis of ground bounce in deep sub-micron circuits,” VLSI Test Symposium, 1997., 15th IEEE, Apr. 27 1997, pp. 110 - 116
[7] Y. M. Jiang, K. T. Cheng, A. C. Deng, “Estimation of Maximum Power Supply Noise for Deep Sub-Micron Designs,” in Proc. Int. Symp. on Low Power Electronics and Design, Aug. 10-12, 1998, pp. 233-238
[8] T. Murayama, K. Ogawa, H. Yamaguchi, “Estimation of peak current through CMOS VLSI circuit supply lines,” Design Automation Conference, vol.1, Jan. 18-21 1999, pp. 295 – 298
[9] Y. J. Wang, “Nanometer CMOS on Chip Serial Link Transmitter”, Master dissertation, Dept. of Electrical Engineering, N.C.U., Taiwan, ROC, July 2005
[10] A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy., “Skewed CMOS: Noise-tolerant high-performance low-power static circuit family,” IEEE Trans. VLSI Syst., vol. 10, issue: 4, pp. 469-476, Aug. 2002.
[11] L. McMurchie, S. Kio, G. Yee, T. Thorp, and C. Sechen, “Output prediction logic: a high-performance CMOS design technique,” Proc. Intl. Conf. Computer Design, 2000, pp. 247-254
[12] P. Larsson, “Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance,” IEEE Trans. on CAS-I, pp. 849-858, Aug. 1998
[13] S. J. Jou, S. H. Kuo, J. T. Chiu and V. Lin, “Low Switching Noise and Load Adaptive Output Buffer Design Techniques,” IEEE Journal of Solid-State Circuits, vol.36, no.8, pp.1239-1249 (SCI, EI), Aug. 2001
[14] N. R. Shanbhag, ”Reliable and efficient system-on-chip design”, IEEE Computer,. vol. 3, issue: 3, pp. 42-50, March 2004.
[15] Y. W. Chiu, “Standard Cell Library Characterization and Mixed-Threshold Voltage Cell Library Design”, Master dissertation, Dept. of Electrical Engineering, N.C.U., Taiwan, ROC, July 2006
[16] N. H. E. Weste, D. Harris, ”CMOS VLSI Design,” 3rd ed., New York: Addison Wesley, 2005, pp. 773-775
[17] W. Dally and J. Poulton, “Digital Systems Engineering,” Cambridge, UK: Cambridge University Press, 1998
[18] P. Larsson, “Parasitic resistance in an MOS transistor used a on-chip decoupling capacitance,” JSSC, vol. 29, no. 6, June 1994, pp. 723-726
[19] G. Ji, T. Arabi, G. Taylor., et. al., “Design and Validation of a Power Supply Noise Reduction Technique,” Electrical Performance of Electronic Packaging, Oct. 2003
[20] T. J. Gabara, W. C. Fischer, J. Harrington, W. W. Troutman, “Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers,” IEEE Journal of Solid State Circuits, vol. 32, no.3, pp. 407-418, Mar. 1997
[21] G. Keskin, X. Li and L. Pileggi, “Active Suppression of Power Supply Noise,” published in CICC 2006
[22] M. L. Yu, “Analysis, Design and Measurement of Low-Energy Clocked Storage Element”, Master dissertation, Dept. of Electrical Engineering, N.C.U., Taiwan, ROC, Jan. 2006