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研究生: 陳彤伊
Tong-Yi Chen
論文名稱: HF頻帶無線供電植入式系統之高效率前端電路分析與設計
Analysis and Design of an Efficient Front-End Circuitry for Wirelessly-Powered HF-Band Implantable Systems.
指導教授: 薛木添
Muh-Tian Shiue
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度: 95
語文別: 中文
論文頁數: 64
中文關鍵詞: 視網膜晶片ASK調變低壓降穩壓器
外文關鍵詞: retinal prosthetic, minute CDR, ASK demodulator, low drop-out regulator
相關次數: 點閱:12下載:0
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  • 本論文提出了一個HF頻帶的無線傳輸前端電路,適用於植入式晶片,特別是針對需要高資料傳輸速率的植入式晶片,如人工視網膜輔具、人工電子耳、多通道微刺激系統等等;使用無線方式傳輸電源、控制晶片的訊號將可避免其它傳輸方式的缺點,如有線式的傷口感染、以及電池式的電源耗盡情形發生。
    本架構將以人工視網膜輔具的前端電路為主,分為兩部分,第一部分是產生電源的電路,使用混合型整流電路以及低壓降穩壓器(Low Drop-out Regulator,LDO),不但可使用較少的晶片面積同時亦可達成降低電源雜訊影響之功效;第二部分是時脈與資料的回復電路,此部分將首先提出一種新ASK解調器,有低調變索引(modulation index)以及高調變比率(modulation rate)的特性,因此可以有效提升解調效能,以及操作在高資料傳輸速率下。


    A wirelessly powered HF-band front-end circuitry is proposed in this thesis. The circuitry is suitable for implantable systems, especially in the case of the designs aspiring to high data-rate transmission, such as retinal prostheses and cochlear implants etc. Using wireless transmission can prevent the problems of infection and frequent replacement of battery.
    The application of the proposed front-end circuitry focuses on the retinal prostheses. The circuitry can be divided into two major parts: The first part includes a hybrid rectifier and a low drop-out regulator, which can reduce the chip area and the noise from the carrier signal. The second part is a minute clock and data recovery (CDR) system in which a new ASK demodulator is involved. Our demodulator features low modulation index and high modulation rate. Therefore it can not only decrease the design space but also increase the demodulation efficiency of the implant.

    摘要 i Abstract ii 目錄 iii 圖目錄 iv 表目錄 vii 第一章 緒論 1 1-1 前言與背景 1 1-2 研究動機 2 1-3 系統架構 3 1-4 系統規格 4 第二章 植入式晶片之前端電路回顧 6 2-1 植入式晶片前端電路 6 2-1-1 整流器電路原理 6 2-1-2 穩壓器電路原理 11 2-1-3 電源啟動重設訊號電路原理 15 2-1-4 解調器電路原理 17 第三章 植入式晶片之前端電路設計 29 3-1 電源管理電路設計 29 3-1-1 整流器 29 3-1-2 穩壓器 33 3-1-3 電源啟動重設電路設計 44 3-2 時脈與資料恢復電路設計 47 3-2-1 解調器 48 3-2-2 解碼器 56 第四章 結果與總結 61 4-1 系統模擬結果與晶片佈局圖 61 4-2 總結與未來發展 64 參考文獻 65

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