此論文主要設計一主被動整合接收器，應用於Ka-Band短距離脈衝雷達的接受器部分，總共完成了四個電路，第一顆提出一個利用90 nm CMOS製程之低成本之35-GHz功率偵測器電路，裡面包含了35-GHz 低雜訊放大器、35-GHz 偵測器兩大電路。在低電壓、低功率的要求下，量測後能提供300K等級的Responsivity且在1 Gb/s調變訊號下有50%以上的Duty cycle，雜訊等效功率也有12.6 fW/√Hz，並且在後續計畫的要求下，我們提出第二顆電路在低雜訊放大器前加入切換器，並且在偵測器後方加入五級中頻放大器，最終接收機輸出端在1GHz的調變下有6 GV/W 的電壓響應度 且雜訊等效功率低於3.5 aw/√Hz。

接下來在第三顆提出一個低成本之35-GHz主被動整合接收器，利用90 nm CMOS製程，電路架構包含了35-GHz三級的低雜訊放大器、雙平衡吉伯特混頻器、差動放大器、偵測器等電路，其電壓響應度達到1.2 MV/W，雜訊等效功率也有12 fW/√Hz，轉換增益有34.4 dB，雙邊帶雜訊指數為7.6 dB。接下來的電路為了在低輸入能量，卻需偵測到約0 dBm得訊號要求下，提出第四顆電路，在電路最前端加入Switch量測隔離度和輸入損耗以方便日後須整合TX的需求，在低雜訊放大器部分加入一級疊接放大器，之後加入差動放大器，使得電路分為兩路：一路為偵測器與中頻放大器，一路為混頻器，整體的結果有達到1Gb/s調變訊號下有50%以上的Duty cycle，且Vpp可達到約1 V，並且在輸出100 MHz 的中頻訊號可達到45 dB 的轉換增益與雙邊頻帶雜訊7.6 dB，在偏壓1.2 V 情況下只有45.8 mW之功耗。

此論文主要設計一主被動整合接收器，應用於Ka-Band短距離脈衝雷達的接受器部分，總共完成了四個電路，第一顆提出一個利用90 nm CMOS製程之低成本之35-GHz功率偵測器電路，裡面包含了35-GHz 低雜訊放大器、35-GHz 偵測器兩大電路。在低電壓、低功率的要求下，量測後能提供300K等級的Responsivity且在1 Gb/s調變訊號下有50%以上的Duty cycle，雜訊等效功率也有12.6 fW/√Hz，並且在後續計畫的要求下，我們提出第二顆電路在低雜訊放大器前加入切換器，並且在偵測器後方加入五級中頻放大器，最終接收機輸出端在1GHz的調變下有6 GV/W 的電壓響應度 且雜訊等效功率低於3.5 aw/√Hz。

接下來在第三顆提出一個低成本之35-GHz主被動整合接收器，利用90 nm CMOS製程，電路架構包含了35-GHz三級的低雜訊放大器、雙平衡吉伯特混頻器、差動放大器、偵測器等電路，其電壓響應度達到1.2 MV/W，雜訊等效功率也有12 fW/√Hz，轉換增益有34.4 dB，雙邊帶雜訊指數為7.6 dB。接下來的電路為了在低輸入能量，卻需偵測到約0 dBm得訊號要求下，提出第四顆電路，在電路最前端加入Switch量測隔離度和輸入損耗以方便日後須整合TX的需求，在低雜訊放大器部分加入一級疊接放大器，之後加入差動放大器，使得電路分為兩路：一路為偵測器與中頻放大器，一路為混頻器，整體的結果有達到1Gb/s調變訊號下有50%以上的Duty cycle，且Vpp可達到約1 V，並且在輸出100 MHz 的中頻訊號可達到45 dB 的轉換增益與雙邊頻帶雜訊7.6 dB，在偏壓1.2 V 情況下只有45.8 mW之功耗。

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