單電子電晶體因具有高電荷靈敏度以及低消耗功率的潛能優點而被受矚目，且被認為在未來可應用於記憶體、邏輯電路以及量子電腦的發展。本論文針對垂直式與平面式的鍺量子點單電子電晶體結構的研製以及電流特性分析做探討。目前本研究團隊已可在在複晶矽鍺的孔洞中利用氧化來達到鍺量子點的定位與定量。我們可藉由低壓化學氣相沉積系統能夠精準控制薄膜厚度的優點沉積二氧化矽與氮化矽側壁的穿隧介電層，並使元件中的鍺量子點自動對準到電極。進而改善自我對準電極元件因電子束微影曝寫時造成奈米線抖動而無法掌控量子點位置與穿隧介電層厚度的缺點。

Single-electron transistors （SETs） have attracted a lot of attention for its potential advantages of high charge sensitivity and low power consumption, which would offer
great potentials for memory-devices, logic-devices and quantum computing in the future. In this thesis, we have studied the fabrication and electrical characterization of Ge QD SETs in vertical and planar structures. We are able to bridle the position and the number of Ge QDs by oxidizing poly-SiGe in a nano-cavity. The Ge QDs are
self-aligned to adjacent electrides via SiO2 or Si3N4 spacers, which also behave as tunnel barriers and whose thickness are directly determined by the thin-film deposition in CVD.

參考文獻
[1] K. K Likharev, “Correlated discrete transfer of single electrons in ultrasmall tunnel junctions, ” IBM J. Res. Develop., vol. 32, p. 144-158, 1988
[2] 陳啟東，「單電子電晶體簡介」，物理雙月刊，第二十六卷，第三期，483－490頁，2004年6月。
[3] T. A. Fulton and G.J. Dolan, “Observation of Single-Electron Charging Effects in Small Tunnel Junction,” Phys. Rev. Lett., vol. 59, p. 109, 1987.
[4] S. W. Hwang et al., “Fabrication and room-temperature characterization of a silicon self-assembled quantum-dot transistor,” Phys. Rev. Lett., vol. 73, p. 3129, 1998.
[5] L. Zhuang, L. Guo and S. Y. Chou, “Silicon single-electron quantum-dot transistor switch operating at room-temperature,” Appl. Phys. Lett., vol. 72, p. 1205, 1998.
[6] Y. Ono et al., “Fabrication method for IC-oriented Si single-electron transistors,” IEEE Trans. Electron Device, vol.47, p. 147-153,2000
[7] M. Saitoh and T. Hiramoto, “Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic resistance,” J. Appl. Phys., vol. 91, p. 6725-6728, 2002
[8] M. Saitoh, H. Harata and T. Hitamoto, “Room-temperature demonstration of integrated silicon single-electron transistor circuit for current switching and analog pattern matching,” in IEDM Tech Dig. 2004, P. 187.
[9] S. Lee, K miyaji, M. Kobayashi, and T. Hitamoto, ”Extremely high flexibilities of coulomb blockade and negative differential conductance oscillations in
room-temperature-operating silicon single hole transistor,” Appl. Phys. Lett., vol. 92, p. 0735021-0735023, 2008
[10] M. Kobayashi, and T. Hitamoto, ”Experimental study on quantum confinement effects in silicon nanowire metal-oxide-semiconductor field-effect transistors and
single-electron transistors,” J. appl. Phys., vol.103, p. 0537091-0537096, 2008
[11] Yi shi et al., “Silicon single electron transistors aiming at a high gate modulation factor,” Appl. Phys. Lett., vol. 89, p. 173135, 2006
[12] Y. Meada, N. Tsukamoto, Y Yazawa, Y. Kanemitsu, and Y. Masumoto, “Visible photoluminescence of Ge microcrystals embedded in SiO2 glassy matrices,” Appl.
Phys. Lett., vol. 59, p. 3168-3170, 1993
[13] K. H. Chen, C. Y. Chien and P. W. Li, “Precise Ge quantum dot placement fot quantum tunneling devices,” Nanotechnol., vol. 21, p. 055302, 2009
[14] P. W. Li et al., ”Fabrication of a germanium quantum-dot single-electron transistor with large coulomb-blockade oscillations at room-temperature,” Appl. Phys. Lett.,
vol. 85, p. 1532, 2004.
[15] P. W. Li et al., ”Study of tunneling currents through germanium quantum-dot single-hole and –electron transistors,” Appl. Phys. Lett., vol. 88, p. 213117, 2006.
[16] G. L. Chen, David M T Kuo, W. T. Lai and P. W. Li, “Tunneling Spectroscopy of germanium quantum dot in single-hole transistors with self-aligned electrodes,”
Nanotechnol., vol. 18, p. 475402, 2007
[17] B. J. Baliga, Power Semiconductor Device, PWS publisher, Boston,1996
[18] 徐紹華, ”具有自我對準下閘電極鍺量子點單電洞電晶體之研製,” 國立中央大學, 碩士論文, 2007年.