隨著主流單晶片系統設計(system-on-chip, SoCs)的複雜度日益提升，以及因應逐漸縮短的緊迫上市時間(time-to-market)，晶片設計者可能缺乏時間成本反覆進行完整的測試。此外，類比與數位混合訊號(analog and mixed signal, AMS)元件在SoC晶片中的地位越來越重要，據統計所佔比重約有30~50%，且有高達50%的驗證錯誤是源自於類比混合訊號區塊，需要消耗時間與成本進行再設計(redesign)。基於上述的理由，系統層級的驗證在現今的設計流程中扮演極重要的角色。
為了加速類比混合訊號電路的驗證，現行常見的解決方法為提升電路階層層級(hierarchy)，使用硬體描述語言(hardware description language, HDL)建立小區塊電路的行為模型(behavioral model)。現存的行為模型研究大多侷限於特定電路架構，如：鎖相迴路(Phase Locked Loop, PLL)、運算放大器(Operational Amplifier, OPA)或射頻傳輸線(RF transmission line)等重複性高的折疊式(cascode)電路；至於電路區塊間用來溝通訊號的連結邏輯(glue logic)，則較少文獻著墨於此種非特定架構模型產生器(model generator)的方法研究。
有鑑於此，本論文致力於行為模型產生器的建構，透過輸入電晶體層級的電路描述，取得電路的初始行為，再經過一連串的電路資訊分析與訊號流上的架構辨識，最終自動產出Verilog語言編寫成的近似行為模型，且與原電路行為的差異控制在很小的誤差範圍內。

With the ever-increasing complexity of system-on-chip (SoCs) and the rapidly decreasing time-to-market, IC designers may not afford repeated full testing. Besides, the proportion of analog and mixed signal (AMS) elements in current SoCs has risen to 30 to 50%, and about 50% of errors that required redesign are owing to AMS parts. As a result, system-level verification takes an important role in today’s industry design flow.
To speed up the co-simulation of AMS circuits, modeling circuit blocks by hardware description languages is a common trend to give rise to hierarchy. An abundance of methodology has been proposed to deal with application specific integrated circuit (ASIC) modeling, such as PLL, OPA, or cascade circuits like RF transmission line. However, there’s few approach concerning about the modeling of glue logics, which are simple logicsor unspecific small circuit blocks used to connect complex circuits together.
This thesis presents a model generator, using simple methods to extracting behaviors from transistor-level descriptions. By analyzing circuit information from recognized structures along signal graph, this model generator eventually produces approximated behavioral model in Verilog within tolerable error range.

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