| 研究生: |
白健永 Chein-Yung Pai |
|---|---|
| 論文名稱: |
三閘極金氧半場效電晶體的二維電位模擬與三維I-V探討 Potential Analysis of Two Dimension I-V Discussion of Three Dimension for Triple-Gate MOSFET |
| 指導教授: |
蔡曜聰
Yao-Tsung Tsai |
| 口試委員: | |
| 學位類別: |
碩士 Master |
| 系所名稱: |
資訊電機學院 - 電機工程學系 Department of Electrical Engineering |
| 畢業學年度: | 99 |
| 語文別: | 中文 |
| 論文頁數: | 54 |
| 中文關鍵詞: | 短通道效應 、轉角效應 、三閘極 |
| 外文關鍵詞: | triple gate, corner effect, short channel effects |
| 相關次數: | 點閱:10 下載:0 |
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在本篇論文中,我們利用二維元件模擬器來模擬三閘極元件內部的電位分布以及電場分布情況,並且討論三閘極元件的轉角效應,同時也使用Poisson’s Equation推導三閘極元件二維內部的電位分布情況,並且將此推導結果與我們利用二維元件模擬器得到的模擬結果做比較,再利用此結果推出模擬與推導的臨界電壓。再者,為了更了解電流的特性曲線I_D-V_G、次臨限擺幅、汲極導致能障降低等短通道效應,我們使用三維元件模擬器,分析三閘極與單閘極元件的I_D-V_G,以及單閘極與三閘極在不同通道長度下次臨限擺幅差異。
In this thesis, we design a 2-D device simulator to simulate the triple gate’s potential distribution and electron distribution , then discuss the corner effect of triple gate’s structure. We add Poisson’s Equation to analyze 2-D potential distributions and simulation, using the formula to compare with the simulation, and use the formula to obtain threshold voltage. In order to understand the characteristics I_D-V_G of device and subthreshold swing and DIBL characteristic, we add 3-D device simulator to analyze the short channel effects about triple-gate structure.
[1]J. P. Colinge, “FinFETs and Other Multi-Gate Transistors, ” Springer, 2008 (Chapters 1–3).
[2]D. A. Neaman, “Semiconductor Physics and Devices: Basic Principles,” Chapter.4, p.155, McGraw-Hill Companies, 2003.
[3]J. G. Fossum, J.-W. Yang, and V. P. Trivedi, “Suppression of corner effects in triple-gate MOSFETs,” IEEE Electron Device Lett., vol. 24, no. 12, pp. 745–747, Dec. 2003.
[4]K. K. Young, “Short-channel effect in fully depleted SO1 MOSFETs, ”IEEE Trans. Electron Devices, vol. ED-36, no. 2, pp. 399–402, Feb.1989.
[5]F. J. Garc?a Ruiz , A. Godoy , F. G?miz , C. Sampedro, and L. Donetti “A comprehensive study of the corner effects in Pi-Gate MOSFETs including quantum effects, ” IEEE Trans. Electron Devices, vol. 54, p.3369 , 2007.
[6]M. G. C. de Andrade and J. A. Martino, “Threshold voltages of SOI MOSFETs,” Solid-State Electron, vol. 52, p.1877 , 2008.
[7]A. Ortiz-Conde, E. D. Gouveia Fernandes, J.J. Liou, M.R. Hassan, F.J.G. S?nchez, and G. De Mercato., “New approach to extract the threshold voltage of MOSFETs,” IEEE Trans Electron Devices 44 (9) (1997), pp. 1523–1528.
[8]P. C. H. Chan and C. T. Sah, “Exact Equivalent Circuit Model for Steady-state Characterization of Semiconductor Devices with Multiple-Energy-Level Recombination Centers,” IEEE Transactions Electron Devices, vol. ED-26, no. 6, pp. 924-936, 1979.
[9]K. Mayaram and D. O. Pederson, “Coupling Algorithms for Mixed-Level Circuit and device Simulation,” IEEE Transactions on Computer-Aided Design, vol. 11, no.8, 1992.
[10]M. G. C. de Andrade and J. A. Martino, “Threshold voltages of SOI MOSFETs,” Solid-State Electron, vol. 52, no. 12, pp. 1877–1883, Dec.2008.
[11]D. J. Foster, “Subthreshold currents in CMOS transistors made on oxygenimplanted silicon,” Electronics Letters, 19-17, 684 (1983)
[12]J. P. Colinge , “Multiple gate SOI MOSFETs,” Solid-State Electron, vol. 48, no. 6, pp. 897–905, Jun. 2004.