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研究生： 陳偉志
Wei-Chih Chen
論文名稱： 全通網路相位偏移器之設計與製作
Design and Fabrication of Phase Shifters Based on All-Pass Networks
指導教授： 傅家相
Jia-Shiang Fu
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 100
語文別： 中文
論文頁數： 72
中文關鍵詞： 可變電容 、鐵電材料 、相位偏移器 、全通網路
外文關鍵詞： Varactor, Ferroelectric, Phase Shifter, All-Pass Network
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    • 本論文使用全通網路架構作為基礎來實現數位式與類比式相位偏移器。在第二章中，我們推導出數位式全通網路相位偏移器的設計公式，並成功地使用穩懋0.15-μm砷化鎵假性高速電子移動場效電晶體製程實現一5.8 GHz 90°相位偏移器晶片。其在設計頻率5.8 GHz 下的量測結果顯示，當電晶體在開與關的狀態下（電晶體閘極偏壓分別為0 V 與−2 V），其插入損耗分別小於1.9 dB 與0.8 dB，而輸入與輸出返回損耗則 大於15 dB，相位偏移量可達88°，與設計目標90°相當接近。
    第三章中我們分析了類比式全通網路相位偏移器，並推導出其設計公式。而為了實現類比式的相位偏移器，我們發展了鐵電可變電容製程。鐵電可變電容中的鐵電薄膜是使用脈衝雷射沉積技術來製作。製作出的可變電容在4 V 偏壓下可達到2:1 的可調度，其於1.8 GHz 時的品質因子大於40。

    In this thesis, digital and analog phase shifters are designed based on all-pass networks.
    In Chapter 2, the design equations for digital all-pass phase shifters are derived. Based on the equations, we successfully implement a 5.8-GHz 90°digital phase shifter chip using WIN 0.15-μm GaAs pHEMT process. The measurement results at 5.8 GHz show that, when the switch is switched to ON and OFF-states (gate terminals of the transistors are biased at 0 V and −2 V, respectively), the insertion loss of the circuit is less than 1.9 dB and 0.8 dB, respectively, and both the input and output return losses are greater 15 dB. The measured phase shift is 88°, which is close to the target phase shift of 90°.
    In Chapter 3, we analyze analog phase shifters based on all-pass networks, and derive the design equations. In order to implement the analog phase shifter, we develop
    ferroelectric variable capacitor (varactor) process. The ferroelectric thin films used in the varactors are fabricated using pulsed laser deposition (PLD) technique. The fabricated ferroelectric varactors can achieve a 2:1 tunability under a bias voltage of 4 V, and possess a
    quality factor greater 40 at 1.8 GHz.

    目錄 摘要 ........................................................................................................................................... i Abstract ...................................................................................................................................... ii 誌謝 .......................................................................................................................................... iv 目錄 ......................................................................................................................................... vii 圖目錄 ....................................................................................................................................... x 表目錄 .................................................................................................................................... xiii 第一章 緒論 .............................................................................................................................. 1 1-1 研究動機 ................................................................................................................... 1 1-2 文獻回顧 ................................................................................................................... 3 1-2-1 向量調節式 ................................................................................................... 4 1-2-2 負載反射式相位偏移器 ............................................................................... 5 1-2-3 分佈式相位偏移器 ....................................................................................... 5 1-2-4 切換式相位偏移器 ....................................................................................... 6 1–3 全通網路 .................................................................................................................. 8 1-4 章節介紹 ................................................................................................................. 11 第二章 全通網路之數位式相位偏移器設計 ........................................................................ 12 2–1 全通網路數位式相位偏移器設計 ........................................................................ 12 viii 2–2 5.8 GHz 數位式全通網路90°相位偏移器晶片設計 ........................................... 15 2–3 模擬與量測結果比較及偵錯 ................................................................................ 18 2–4 結果與討論 .............................................................................................................. 24 第三章 全通網路之類比式相位偏移器設計與鐵電可變電容製作 .................................... 25 3–1 全通網路之類比式相位偏移器 ............................................................................ 25 3–2 1.8 GHz 全通網路類比式相位偏移器設計與模擬 .............................................. 28 3–3 可變電容技術 ........................................................................................................ 31 3–4 鐵電材料與溫度關係 .............................................................................................. 33 3–5 鐵電可變電容 .......................................................................................................... 35 3–5–1 鐵電可變電容製作 ...................................................................................... 35 3–5–2 鐵電薄膜成長條件 .................................................................................... 38 3–6 鐵電可變電容特性 .................................................................................................. 41 3–7 結論與討論 .............................................................................................................. 47 第四章 結論 ............................................................................................................................ 48 參考文獻 ................................................................................................................................. 49 附錄A ..................................................................................................................................... 52 雙埠對稱網路奇偶模對稱分析 ...................................................................................... 52 附錄B ..................................................................................................................................... 53 B.1 Bottom electrode evaporation and liftoff. .................................................................. 53 ix B.2 Ferroelectric thin film deposition by PLD. ................................................................ 53 B.3 Top electrode evaporation and liftoff. ........................................................................ 54 B.4 Ferroelectric thin film wet etch. ................................................................................. 54

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