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研究生： 翁盟智
Meng-Tzer Wong
論文名稱： 2.5Gbps CMOS串列式傳輸收發器設計
A 2.5Gbps CMOS Serial Link Transceiver Design
指導教授： 陳巍仁
Wei-Zen Chen
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 90
語文別： 中文
論文頁數： 100
中文關鍵詞： 串列 、收發器 、傳送器 、接收器
外文關鍵詞： receiver, transmitter, transceiver, serial link
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    • 隨著網際網路資料傳輸速度的與日遽增，低成本高速串列式傳輸技術亦隨之蓬勃發展。串列式收發器的應用相當廣，可應用在光纖網路、萬用串列匯流排(USB)、IEEE-1394、TMDS等系統。傳統上，收發器多使用昂貴的砷化鎵製程，今日，數十億赫茲的射頻積體電路已經成功地使用深次微米CMOS和BicMOS製程實現出來。為了降低製程元件成本，本論文探討使用0.35微米矽製程來實現收發器之相關電路設計技術，其具體目的在達成每秒2.5十億位元(2.5Gbps)的串列式收發器電路。
    在傳送端方面，本論文提出一個2伏、每秒2.5十億位元(2.5Gbps)的CMOS資料串列傳輸器。藉由一個低抖動和八個相位的鎖相迴路對多工器做時間區分，可將平行的資料轉換成串列的訊號。本論文提出一個可預先充電的多工器，用以減少多工器造成的抖動。
    在接收端方面，本論文提出一個使用3倍超取樣技術的資料回復器，其功能是將串列的訊號轉換回平行的資料。藉由鎖相迴路和內插器產生的相位，可對串列訊號做3倍取樣，此資料回復器不僅可決定出最佳的取樣點、亦可找到資料的起始位置，還可以處理頻率偏移的問題。本論文在內插器裡用了平均的技巧，可以產生更精準的相位分佈，而在決定最佳取樣點方面，則使用電流控制數位類比轉換器(current-steering DAC)的架構來減小設計的複雜度、整體面積以及延遲的時間。
    在傳送端，其最大的轉換速率超過每秒312.5百萬位元組(312.5Mbytes/s)，並且可達到2.5十億位元(2.5Gbps)的傳輸速度，經量測的結果，均方根抖動小於6ps，其眼圖符合OC-48的要求，晶片面積為1062微米 * 1020微米。
    在接收端，其鎖相迴路的頻率範圍可由80百萬赫茲(80MHz)至450百萬赫茲(450MHz)，輸入串列訊號頻率為每秒2.5十億位元(2.5Gbps)，可輸出八個每秒312.5百萬位元(312.5Mbps)的平行資料，還可處理2.5百萬赫茲(2.5MHz)的頻率偏移，整個核心電路操作在2伏電壓，而輸入及輸出的緩衝器操作在3伏電壓，所有功率消耗約280毫瓦，全部面積約2.9毫米 *2.4毫米。


    In transmitter design, a 2V and 2.5Gbps CMOS data serializer has been proposed. High speed parallel to serial data conversion is achieved by means of time-division multiplexer toggled by a low jitter 8-phases phase-locked loop. This thesis proposes a precharge multiplexer to reduce jitter.
    At the receiver side, a 3* oversampling data recovery is described. The utility of data recovery is to convert serial signal back to parallel data. The serial signal is sampled by phases which are generated by a phase-locked loop and interpolators. This data recovery not only finds the optimal sampling points and the start of data, but also handles the problem of frequency offset. This thesis proposes the interpolators with average resistors in order to generate phases more accurately. In finding optimal sampling points, this thesis uses the architecture of current steering digital-to-analog converter. This implementation decreases the complication of circuit design, entire area, and latency.
    The transmitter achieves a conversion rate up to 312.5Mbyte/s and a transmission speed of 2.5Gbps. The measured RMS jitter is less than 6ps from a 2.5Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062um * 1020um.
    In the receiver design, the frequency range of phase-locked loop is from 80MHz to 450MHz. The frequency of input serial data is 2.5Gbps, and the frequencies of output 8 parallel data are 312.5Mbps. The latency from input to output is 102.4ns. This data recovery can handle 2.5MHz frequency offset. Core circuits are operated under a 2V supply and input and output buffers are operated under a 3V supply. Total power consumption is about 280mW, and the entire area is about 2.9mm * 2.4mm.

    Abstract 1 Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Transceiver Architecture 1 1.3 Thesis Organization 4 Chapter 2 Phase-Locked Loop 6 2.1 Introduction 6 2.2 PLL Architecture 7 2.3 PLL Linear Model 7 2.4 PLL Architecture for Transmitter 9 2.4.1 Phase Frequency Detector 9 2.4.2 Charge Pump 10 2.4.3 Loop Filter 11 2.4.4 4-Stage Voltage Controlled Oscillator 12 2.4.5 Divider 15 2.5 Measurement of PLL for transmitter 16 2.6 PLL Architecture for Receiver 19 2.6.1 6-stage Voltage Controlled Oscillator 19 2.6.2 Interpolator 21 Chapter 3 Data Serializer 25 3.1 Introduction 25 3.2 Data Serializer Architecture 25 3.2.1 Data Serializer with Multi-Stage Multiplexers 26 3.2.2 Data Serializer with a N-to-1 Multiplexer 26 3.3 Building Blocks of Data Serializer 27 3.3.1 Parallel-In-Serial-Out Multiplexer 28 3.3.2 Output Buffer 30 3.4 MEASUREMENT RESULT 32 Chapter 4 Jitter Analysis 35 4.1 Introduction 35 4.2 Jitter Analysis in PLL-Based CDR 36 4.3 Jitter Analysis in Oversampling-Based CDR 44 Chapter 5 Clock/Data Recovery 48 5.1 Introduction 48 5.2 Data Recovery Architecture 48 5.2.1 PLL-Based Data Recovery 49 5.2.2 Oversampling-Based Data Recovery 50 5.3 Multiple-Phase Clock Generation 51 5.4 Oversampling Circuit Design 51 5.4.1 Input Buffer Design 52 5.4.2 Preamplifier Design 53 5.4.3 Comparator Design 54 5.4.4 SR-Latch Design 55 5.4.5 Simulation of Oversampling Circuit 56 5.5 Phase Decision 57 5.5.1 Phase Decision Algorithm 57 5.5.2 Phase Decision Architecture 60 5.5.3 Phase Decision with Current-Steering DAC 62 5.6 Preamble Detector 65 5.7 Frequency offset 66 5.7.1 Byte Align Circuit 70 5.7.2 First-In-First-Out Buffer 73 5.8 Layout and Simulated Results 78 5.9 Measurement Considerations 81 Chapter 6 Conclusion & Future Work 83 6.1 Conclusion 83 6.2 Future Work 84 References 85

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