In this thesis, a design methodology for Booth-encoded Montgomery''s modular multiplication algorithms is proposed. The new design methodology helps us to re-duce the required iteration number in the Encryption/Decryption of RSA cryptosys-tem. With application of pipelining and folding/unfolding techniques to the design of Montgomery''s modular multiplication module, we construct the processing element (PE) called M-cell. With the M-cell''s, we can easily reconfigure the RSA chip. It is very convenient to reconfigure the RSA chip for different specification by cascade different number of M-cells and reuse them. The final optimized Montgomery''s modular multiplication module is a digit-serial, pure-systolic, and scalable architec-ture with 100% utilization of all PE modules. The simulation result shows that we can not only reduce the required iteration number from 2n^2 to n^2 using H algorithm, hard-ware complexity is also simplified. The efficiency (time-area product) of our design is improved about a factor of 2.5. The simulation results show that the maximum speed-performance of single RSA chip can be up to 476kbit/sec.

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