矽基低維度熱電量測平台之製備與研究｜國立中央大學博碩士論文系統

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研究生：	蔣明勳 Ming-Xun Jiang
論文名稱：	矽基低維度熱電量測平台之製備與研究 Batch fabrication and thermoelectrical Measurement of Si-based thermoelectric device in low dimension
指導教授：	李勝偉 Sheng-Wei Lee
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 材料科學與工程研究所 Graduate Institute of Materials Science & Engineering
論文出版年：	2016
畢業學年度：	104
語文別：	中文
論文頁數：	72
中文關鍵詞：	矽奈米緞帶結構、熱電量測平台、半導體製程、量子點
外文關鍵詞：	silicon nanoribbon structure, thermoelectric measurement platform, semiconductor process, quantum dots
相關次數：	點閱：9 下載：0
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自從工業革命後，人類社會大量使用石化燃料，除了造成許多汙染外，亦會產生太多無法直接利用的廢熱。熱電材料為一種熱能和電能彼此之間可以互相轉換的材料，我們希望以此將無法利用的廢熱轉化為可以使用的電能。近年來，許多研究指出低維度半導體材料和表面粗糙度可以增加熱電材料轉化效率的評估值(ZT值)，因此我們選擇矽(silicon)這種與半導體產業高度相容的材料作為研究對象，將SOI wafer上之矽層以一系列半導體製程(黃光微影、蒸鍍、化學氣相沉積、反應性乾蝕刻……等)製備一量測矽奈米緞帶結構之熱電量測平台，可量測此結構之熱導率、電導率、席貝克係數。隨後量測鍍附矽鍺量子點之表面、選擇性濕蝕刻後之金字塔結構之表面製備的熱電量測微機電系統以探討表面奈米結構對熱電性質之影響。

Since industrial revolution, the fossil fuels is widely used in human society.
It produces much pollution and waste heat we can’t use. Thermoelectrical materials can transform the energy between heat and electric. We wish it can transform the waste heat to electrical force. In this year, there are many research
indicate low-dimensional semiconductor material and surface roughness will increase the ZT value, which can evaluate the thermoelectric conversion efficiency. Therefore, we choose silicon which is highly compatible in semiconductor industry as our research object. After a series of semiconductor process (photolithography, evaporation, CVD, RIE……and so on), the silicon device layer on SOI wafer is batch-fabricated to the thermoelectrical measurement platform of silicon nanoribbon structure. It can measure the thermal conductivity, electrical conductivity, seebeck coefficient. Finally, We study the surface roughness in quantum dots surface and Pyramid structure surface for the thermoelectric property.

摘要    i
Abstract    ii
致謝    iii
目錄    v
圖目錄    ix
表目錄    xii
第一章 緒論    1
1.1熱電文獻回顧    1
1.1.1 發展歷史    1
1.1.2 熱電效應    4
1.1.3熱電優值    7
1.2微機電系統    9
1.3 研究動機    10
第二章 實驗設置    12
2.1實驗藥品    12
2.2.實驗流程    13
2.3實驗製程設備    15
2.3.1雷射光罩製作系統(Laser Direct Write Image System)    15
2.3.2光罩對準曝光機(Mask Aligner System)    15
2.3.3低壓化學氣相沉積系統(Low Pressure Chemical Vapor Deposition system,LPCVD)    16
2.3.4旋轉塗佈機 (Spin Coater)    17
2.3.5反應式離子蝕刻系統(Reactive Ion Etching,RIE)    17
2.3.6 PECVD 電漿輔助化學氣相沉積系統 (Plasma-enhanced chemical vapor deposition)    18
2.3.7高真空電子束暨熱阻式蒸鍍系統 (E-gun &Thermal Evaporation System)    18
2.3.8紫外光臭氧清洗機(UV-Ozone Stripper)    19
2.3.9表面輪廓儀    20
2.3.10 快速熱退火系統 (Rapid Thermal Annealing ,RTA)    20
2.3.11鋁線銲線機    21
2.3.12原子力顯微鏡(atomic force microscope ,AFM)    21
2.3.13 掃描式電子顯微鏡 (Scanning Electron Microscopy)    22
第三章 熱電微機電系統平台製作與量測    26
3.1實驗步驟    26
3.1.1實驗試片準備    26
3.1.2第一道製程    30
3.1.3第二道製程    34
3.1.4第三道製程    35
3.1.5第四道製程    39
3.1.6第五道製程    41
3.1.7 掏空二氧化矽形成懸浮結構    42
3.1.8製備熱電性質量測試片    42
3.1.9熱電性質量測    43
第四章 實驗結果與討論    46
4.1元件製程討論    46
4.2矽奈米緞帶結構熱電性質探討    47
4.2.1矽奈米緞帶結構電性值之探討    47
4.2.2不同表面對材料熱傳導率之影響    48
4.2.3矽奈米緞帶結構熱電性質量測    50
4.3結論    52
第五章 未來展望    53
參考文獻    54

 
圖目錄
________________________________________
圖1.1 Seebeck觀察磁針偏轉所用設備示意圖[3]    2
圖1.2 Seebeck效應示意圖[20]    5
圖1.3 Peltier效應示意圖[21]    6
圖1.4 Thomson 示意圖[22]    7
圖1.5 熱電模型    7
圖1.6 材料電路示意圖    7
圖1.7熱電量測之微機電系統    11
圖2.2實驗流程示意圖    14
圖2.2 MA6 光罩對準曝光機外觀[27]    23
圖2.3 LPCVD 設備結構示意圖[28]    23
圖2.4反應性離子蝕刻原理示意圖[29]    24
圖2.5 電漿輔助化學氣相沉積系統結構示意圖[26]    24
圖2.6紫外光臭氧清洗機原理示意圖    25
圖2.7 鋁線焊線機[30]    25
圖3.1 微積體元件製作示意圖    28
圖3.2濕式氧化後SOI wafer 分層結構示意圖    30
圖3.3第一道光罩示意圖    31
圖3.4光學顯微鏡(OM)下之矽奈米緞帶和矽接墊影像    33
圖3.5定義矽奈米緞帶(Si nanoribbon)之幾何結構示意圖    33
圖3.6 利用RIE蝕刻出四點探針電極沉積區域    35
圖3.7第三道製程沉積金屬線圈電阻溫度計之光罩設計圖    38
3.8 金屬掀離製程後光學顯微鏡影像    38
圖3.9 RTA後四點接觸光學顯微鏡之影像    39
圖3.10第四道光罩設計圖    40
圖3.11熱電性質量測之微機電系統SEM圖-1    41
圖3.12熱電性質量測之微機電系統SEM圖-2    42
圖3.13焊線後的金屬接墊示意圖    43
圖3.14量測配置圖    44
圖3.15 鉑線圈電阻對溫隨溫度變化圖    45
圖4.1 元件掏空示意圖    46
圖4.2 不同尺寸之奈米緞帶結構與電阻率之關係圖    48
圖4.3不同表面之矽奈米緞帶之熱導率分布圖    48
圖4.4量子點形成金字塔尖端結構示意圖    50
圖4.5 導電率與溫度之關係圖    51
圖4.6熱導率與溫度之關係圖    51
圖4.7席貝克係數與溫度之關係圖    52
















表目錄
________________________________________
表2.1實驗藥品    12
表3.1 SOI wafer規格    26
表3.2 LPCVD 濕式氧化參數表    29
表3.3 第一道製程反應性離子蝕刻參數列表    33
表3.4 第二道製程低壓化學氣相沉積矽統參數列表    34
表3.5 第二道製程反應性離子蝕刻參數列表    35
表3.6 第三道製程高真空電子束暨熱阻式蒸鍍系統蒸鍍參數    37
表3.7 第四道製程反應性離子蝕刻參數列表    40
表3.8第五道製程反應性離子蝕刻參數列表    41
表4.1氮化矽薄膜溼式蝕刻率(S:幾乎可忽略)    47





                                

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