隨著資料的傳輸頻寬不斷上升，而晶片與晶片間之通道頻寬並未隨之上升，資料將無法維持良好之訊號完整度，因此等化器被廣泛應用於接收端以補償資料經過通道產生的衰減，本論文參考USB3.0之規格實現具自無限脈衝響應及離散時間技術之5 Gb/s決策回授等化器電路。
由於通道之頻率響應特性為隨著資料傳輸速率上升，通道衰減量隨之線性增加，因此高速串列傳輸系統所面臨到的之通道衰減量變得不容小覷。對此較大之通道衰減量，若完全採用離散時間決策回授等化器，將造成過大之功率消耗。反之，若單純使用無限脈衝響應決策回授等化器，所面臨到的問題為回授訊號易受到製程及溫度變異而使得等化器產生過補償及欠補償的情況。因此本論文提出同時調整離散時間及無限脈衝響應決策回授等化器之方法，於第一個後游標之位置，藉由改變兩者所佔之權重，得到一個眼圖之最佳解，此方法可使無限脈衝響應決策回授等化器於製程及溫度變異下之眼寬得到最佳解。本論文使用TSMC 90 nm (TN90GUTM) 1P9M CMOS製程來實現，電路操作電壓為1 V，輸入資料為5 Gbps，輸入時脈為5 GHz，在通道衰減量24 dB時，等化後資料的峰對峰值抖動量為45.78 ps，方均根抖動量為8.60 ps;在通道衰減量14 dB時，等化後資料的峰對峰值抖動量為30.22 ps，方均根抖動量為6.05 ps;在通道衰減量7 dB時，等化後資料的峰對峰值抖動量為24 ps，方均根抖動量為4.50 ps。在通道衰減24 dB下之整體功率消耗為9.8 mW，其中決策回授等化器電路之功率消耗為5.4 mW，自適應機制電路之功率消耗為4.4 mW。晶片面積為0.868 mm2，核心電路面積為0.037 mm2。

As the data rate increasing, the signal integrity of high speed data transmission is worse since the limiting bandwidth of channel. Therefore, receivers generally adopt an equalizer to compensate for the signal attenuation caused by the channel. This study presents a 5 Gb/s adaptive infinite-impulse-response decision-feedback equalizer with infinite-impulse-response decision-feedback equalizer (IIR-DFE) and discrete-time decision-feedback equalizer (DT-DFE) Techniques, and takes USB 3.0 specification as reference material.
As the data rate increases, the channel loss increase linearly. Therefore, the channel loss should not be underestimated in the high speed serial link system. The power consumption becomes prohibitive if the equalizer fully adopts the DT-DFE technique for this larger channel loss. On the contrary, the feedback signal is easily affected by the process and temperature variations which cause the over compensation and under compensation if the equalizer fully adopts the IIR-DFE technique. In this thesis, the DT-DFE and the IIR-DFE are simultaneously controlled. This method can make the IIR-DFE get the best eye width under the process and temperature variation, by determining the both weights of two mechanisms to get the widest eye width at the first-post cursor position. This test chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process with 1 V supply voltage. The data rate is 5 Gbps and the DFE is operating at 5 GHz. When channel loss is 24 dB, the peak-to-peak jitter of equalized data is 45.78 ps, the root mean square (RMS) jitter of equalized data is 8.60 ps. When channel loss is 14 dB, the peak-to-peak jitter of equalized data is 30.22 ps, the RMS jitter of equalized data is 6.05 ps. When channel loss is 7 dB, the peak-to-peak jitter of equalized data is 24 ps, the RMS jitter of equalized data is 4.50 ps. The total power consumption of this work is 9.8 mW under 24 dB channel loss, and the power consumption of DFE and adaptive mechanism are 5.4 mW and 4.4 mW, respectively. The chip area is 0.868 mm2 and the core area is 0.037 mm2.

參考文獻
[1] PCI Express® Base Specification, Revision 2.1, PCI-SIG, 2010.
[2] Serial ATA International Organization, Serial ATA Revision 3.0, SATA-IO, 2009.
[3] Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013
[4] 孫世洋, “以符碼間干擾偵測技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2016.
[5] B. Razavi, Design of Integrated Circuits for Optical Communications. McGraw-Hill: Behzad Razavi, 2003.
[6] A. X. Widmer, and P. A. Franaszek, ”A DC-balanced, partitioned-block, 8b/10b reansmission code,” IBM J. Res and Develop., vol. 27, pp. 440-451, Sep. 1983.
[7] S. H. Hall, G. W. Hall, and J. A. McCall, High-speed digital system design-Ahandbook of interconnect theory and design practices, John-Wiley, 1st ed., 2002
[8] Altera Corporation, “Deterministic Jitter (DJ) Definition and Measurement,” 2009
[9] Maxim, “Optical receiver performance evaluation”.
[10] SHF Communication Technologies AG, “Application Note AN-JITTER-1-Jitter Analysis using SHF 10000 Series Bit Error Rate Testers,” 2005.
[11] K.-H. Cheng, Y.-C. Tsai, Y.-H. Wu, and Y.-F. Lin, “A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 57 , no. 5 , pp. 324-328 , May. 2010.
[12] J. Lee, P.-C. Chiang, P.-J. Peng, L.-Y. Chen, and C.-C. Weng, “Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies,” IEEE J. Solid-State Circuits, vol. 50, no. 9, pp. 2061–2072, Sep. 2015.
[13] J. W. Jung, and B. Razavi, “A 25 Gb/s 5.8 mW CMOS Equalizer,” IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 515–526, Feb. 2015.
[14] H. Wang, and J. Lee, “A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 909–920, Apr. 2010.
[15] S. Shahramian and A. C. Carusone, “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722–1735, Feb. 2015.
[16] S. O. Haykin, Adaptive Filter Therory (5th Edition). Prentice Hall, 2002
[17] O. Elhadidy and S. Palermo, “A 10 Gb/s 2-IIR-Tap DFE Receiver with 35 dB Loss Compensation in 65-nm CMOS ,” in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2013, pp. C272–C273.
[18] S. Shahramian, B. Dehlaghi and A. C. Carusone, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 μs,” IEEE J. Solid-State Circuits, vol. 51, no. 1, pp. 3192–3203, Feb. 2016.
[19] Keysight, “M8048A ISI Channels - Data Sheet”.
[20] B. Kim, J. F. Bulzacchelli and D. J. Friedman, “A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44 , no. 12 , pp. 3526 - 3538 , Dec. 2009.
[21] Y.-C. Huang and S.-I. Liu, et al., “A 6Gb/s Receiver with 32.7dB Adaptive DFE-IIR Equalization,” ISSCC Dig. Tech. Papers, pp. 356-357, Feb. 2011.
[22] S. Shahramian, H. Yasotharan, and A. C. Carusone, “Decision feedback equalizer architectures with multiple continuous-time infinite impulse response filters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 6, pp. 326–330, Jun. 2012.
[23] S. Son et al., “A 2.3-mW, 5-Gb/s low-power decision-feedback equalizer receiver front-end and its two-step, minimum bit-error-rate adaptation algorithm,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2693–2704,Nov. 2013.