隨著製程的演進，混合訊號系統的積體電路設計變得越來越複雜，加速類比與數位混合訊號模擬的時間，是現在驗證單晶片系統設計中很重要的一環，以硬體描述語言建立類比電路的行為模型，是一種有效率的混合訊號系統驗證方式，為了將設計者的電路自動轉換成行為模型，在本論文中提出一套有效率的電路架構分析流程，可以自動萃取出混合訊號設計中屬於數位電路的部分，且建構出一個架構分析平台，將Netlist檔案自動轉換成Verilog檔案，將設計的層級從電晶體層級拉到行為階層，達到加速電路模擬的效果，由幾個電路上的實驗結果來看，我們確實能夠正確辨識出對應的電路，並維持模擬結果的準確度。

The design and development of analog/mixed-signal(AMS) integrated circuits is becoming increasingly complex as technologies advances. Speeding up analog and mixed signal simulation is important in SoC design verification. Modeling analog circuit blocks by hardware description language and building their behavioral models is an efficient verification approach for AMS systems. To transform the circuits of designer into behavioral models automatically, in this thesis, we proposed an efficient structure analysis flow that can extract digital circuits in mixed-signal design automatically, and built a structure analysis platform to enable transforming Netlist files to Verilog automatically, replacing transistor-level design with behavior-level design and achieving the propose of speeding up simulation. With those behavioral models, the verification complexity and the simulation time can be reduced significantly. As shown in the experimental results on several circuits, the proposed approach is able to reach correct recognition with good accuracy.

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