果作㆒些介紹與探討。製造MESFET 的傳統製程是利用非自我準直
(non-self aligned)技術，將矽離子佈植到㆒半絕緣(semi-insulating)的
砷化鎵基板㆗，而形成n 型導電層。但由於離子通道效應的影響使
得植入離子的分佈變寬，造成製造出來的元件特性較差。為了克服
此缺點可共同佈植㆒p 型埋層(buried p-layer)來抑制其漏電流(leakage
current) 、降低起始電壓(threshold voltage) 和提高互導值
(transconductance)。所以我們就利用共同佈植(co-implantation)的製程
將矽離子及鎂(Mg)離子或鈹離子(Be)植入至半絕緣的砷化鎵基板
㆗，再以快速高溫熱退火(rapid-thermal annealing)處理，來修復被破
壞的晶格及活化植入的載子。為了瞭解矽離子佈植到半絕緣的砷化
鎵基板，和在共同佈植p 型埋藏層，經不同活化溫度的快速高溫熱
退火處理後載子活化情況。可由霍爾量測(Hall measurement)來測量
樣品活化的載子濃度，藉以得到最佳的活化條件。
由傳輸線模型（Transmission Line Model ,TLM）量測得知，只
有n 型通道層的元件所量得的特徵接觸電阻值最小，為4.8 × 10-7Ω
-cm2。以鈹離子形成p 型埋藏層的元件當閘-源極電壓(VGS)為-2.5V，
整個電晶體已達到夾止狀態， 且在VGS=0V 時有最大互導值
115mS/mm，並有極佳的線性度。在元件的高頻特性量測㆖，以鈹離
子形成p 型埋藏層之元件，電流增益截止頻率( ft ) 為10GHz 及以外
插法求得的功率增益截止頻率( fmax ) 約為39GHz 。兩者皆較以鎂離
子形成p 型埋藏層之元件來的大。
為了改善以鎂離子形成p 型埋藏層的元件無法夾止的問題。我
們將鎂離子的佈值劑量由原先的6× 1011cm-2 提高至2× 1012cm-2，先
由霍爾量測觀察載子濃度的變化，並利用LSS 模擬與電化學-電容電
壓量測，探討晶片㆗載子的分佈情形，以及元件製作之後的特性。
隨著鎂佈植劑量的增加，所量測到的活化載子濃度越來越小。
在最佳活化溫度為850℃，載子濃度已由原先的5.6× 1017減少為3.5×
1017cm-3；數據顯示，當鎂佈植劑量提高，相對的對通道內n型載子
的補償現象愈明顯，而使得通道內n型載子濃度變低。
元件製作完成後發現，當鎂離子的佈植劑量提高至2× 1012cm-2
時，元件無法夾止的問題已獲解決，且在閘極偏壓為零附近有最大
互導值(gm)130mS/mm及最大飽和電流(IDSS)200mA/mm。但由於隨著
p-型摻質數目的增加，對n-型通道載子濃度的降低愈明顯，其接觸
電阻已變差為1× 10-4Ω-cm2。

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