本論文的主題是單級疊接放大器在毫米波頻段的分析及其設計。
我們利用電路模擬軟體找出在不同電晶體大小與不同電晶體閘極偏壓
下我們所需的增益，再設計匹配電路使其有足夠的穩定度與返回損
耗。
在第二章中，我們使用TSMC 0.18-μm CMOS 製程模擬單級疊接
放大器進行分析，我們先固定電晶體的寬度，改變電晶體閘極偏壓和
finger 模擬24 GHz 和35 GHz 時最大可得增益、穩定因子、NFmin、
直流功耗的趨勢。並使用負載拉移模擬得到不同的電晶體尺寸和電晶
體閘極偏壓下和中心頻分別為24 GHz 和35 GHz 時的最大功率增進
效率和最大輸出功率，與其對應的增益和負載阻抗。
在第三章中，我們使用TSMC 0.18-μm CMOS 製程設計一個中心
頻在35 GHz 的單級疊接放大器，在3.3 V 的供應電壓下，期望可有
6 dB 的增益，匹配網路使用L section 的方式設計，匹配電容為MIM
電容，短路殘段的部分則使用全波電磁分析（EM）模擬替代匹配電
感帶入電路中。模擬結果為輸入返回損耗大於20 dB，輸出返回損耗
大於20 dB，增益大於7.6 dB，直流功耗為58.9 mW。。然而量測結
果顯示輸入返回損耗大於16 dB，輸出返回損耗大於3.4 dB，增益大
於3.7 dB，直流功耗為54.45 mW。我們發現造成增益下降的主要原
因可能為輸出損耗比我們預想的大，因此在偵錯的重新模擬中我們在
輸出端串聯一個電感後再重新匹配，重新模擬結果確實能較為貼和量
測結果。
本論文成功設計了單級疊接放大器，雖然量測結果與模擬結果相
去甚遠，但經過重新模擬，已可推測造成此差異的部分原因。

The subject of this paper is the design and analysis of single-stage
cascode amplifiers. We use circuit simulation software to find out the
gain we need under different transistor sizes and different transistor gate
bias voltages, and then design the matching circuit to have sufficient
stability and return loss.
In Chapter 2, we use the TSMC 0.18-μm CMOS process to simulate
a single-stage stacked amplifier for analysis. We first fix the width of the
transistor, change the gate bias voltage of the transistor, and simulate
the maximum gain at 24 GHz and 35 GHz with a finger. Stability,
NFmin, DC power consumption trends. And use load pull simulation
to obtain the maximum power added efficiency and maximum output
power of different transistor size and transistor gate bias and center
frequency of 24 GHz and 35 GHz, respectively, corresponding to them
the gain and load impedance.
In Chapter 3,we use TSMC 0.18-μm CMOS process to design a
single-stage cascode amplifier with a center frequency of 35 GHz. Under
a supply voltage of 3.3 V, it is expected to have a gain of 6 dB.
The matching network uses L section The matching capacitor is a MIM
capacitor, and the part of the short-circuit stub is brought into the circuit
using full-wave electromagnetic analysis (EM) simulation instead
of matching inductance. The simulation result is that the input return
loss is greater than 20 dB, the output return loss is greater than 20 dB,
the gain is greater than 7.6 dB, and the DC power consumption is 58.9
II
mW. . However, the measurement results show that the input return
loss is greater than 16 dB, the output return loss is greater than 3.4
dB, the gain is greater than 3.7 dB, and the DC power consumption is
54.45 mW. We found that the main reason for the decrease in gain may
be that the output loss is larger than we expected. Therefore, in the
re-simulation of debugging, connect an inductor in series at the output
terminal and then re-match. The re-simulation results can indeed be
more consistent with the measurement results.
This paper has successfully designed a single-stage cascode amplifier.
Although the measurement results are far from the simulation
results, after re-simulation, part of the reason for this difference can be
inferred.

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