在此篇論文中，將歷屆學長姊所做的數位信號處理器，依照工研院所提出的矽智財規範，將之矽智財化，提升可重複利用性。在修改的過程中，發覺blocking及non-blocking的使用限制對設計的影響層面最大，也是最不容易修改的。所以在整個設計流程中，開發者若能越早依循矽智財規範來做設計，將來所需額外付出的修正代價就越小。
為了能使多顆處理器在資料的溝通上能更加流暢，不會被輸出入介面限制住，在本篇論文中也提出一個河流式輸出入介面，利用記憶體連線以及累加暫存器連線兩種模式，加速資料的傳遞。
最後利用模組產生器，產生出三顆處理器，彼此之間以河流式輸出入介面相連接，將之應用於正交分頻多工系統中的載波相位追蹤機制，其操作速度分別為60MHz、30MHz及30MHz。

In this thesis, we modify our group''s DSP verilog code for intellectual property and reuse methodology. In order to follow IP qualification guidelines, we rewrite our code and find the rule about blocking and non-blocking is hard to fit. So we should follow SIP guidelines in early stage.
Because our original I/O waste many clock cycles in data communication among several DSPs, we develop stream based I/O for multi-DSP system.Data can be transferred between several DSP smoothly and area overhead is only 6%.
Finally we integrate IP consideration and stream based I/O to DSP generator. Then we use it to generate three DSP for carrier frequency tracking system. The maximum operation frequency of three DSPs are 60MHz, 30MHz, 30MHz.

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