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研究生: 張書豪
Shu-Hao Chang
論文名稱: 具溫度變異補償技術之無參考訊號時脈產生器
A Reference-less Clock Generator with Temperature Variation Compensation
指導教授: 鄭國興
Kuo-Hsing Cheng
口試委員:
學位類別: 碩士
Master
系所名稱: 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 101
中文關鍵詞: 時脈產生器鎖相迴路快速鎖定溫度變異補償
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  • 本論文提出具溫度變異補償技術之無參考訊號時脈產生器,共提出兩個電路架構。第一個為操作頻率為8 MHz之非石英式振盪器,將傳統弛張振盪器的架構進行改良,對於供應電壓以及溫度變異有較佳的抵抗能力,並在脈波產生器對迴路延遲時間做溫度補償。第二個為具多相位輸出,操作頻率為512 MHz及768 MHz之多相位鎖相迴路,其參考訊號源自上述之非石英式振盪器,並在兩個電路之間設計一個溫度補償技術,且加入溫度補償係數之微調電路,確保輸出頻率在不同製程條件下有更高的精準度。
    本論文之實驗晶片是採用180 nm 1P6M CMOS製程。當溫度範圍在 -40 °C到150 °C,此無參考訊號時脈產生器可達到768 MHz,輸出頻率漂移量為13.2 ppm/ °C。在供應電源變異為 ±10 %的範圍內,量測到的輸出頻率漂移量小於 0.08 %。因此本論文之無參考訊號時脈產生器可取代傳統石英振盪器以提供穩定、可靠及低溫度係數之時脈訊號,達到較小面積和低成本的設計。


    A reference-less clock generator with temperature variation compensation is presented, which includes two architectures. The first one is an 8 MHz crystal-less oscillator. It provides higher immunities of temperature and supply voltage variations by improving the conventional relaxation oscillator. A proposed pulse generator is used to eliminate the loop delay time caused by temperature variations. The second architecture is a 512 MHz and 768 MHz multi-phase phase-locked loop, and its reference signal is from the former oscillator. Besides, this work provides a temperature variation compensation technique between the two architectures. It also applies a temperature coefficient calibration circuit to ensure the output frequency has a higher accuracy in the process variations.
    The experimental chip was fabricated by 180 nm 1P6M CMOS process. Under the temperature range from -40 °C to 150 °C, the clock generator output produces a target frequency of 768 MHz and the output frequency drift is 13.2 ppm/°C. Its output frequency drift is less than 0.08 % under the ±10 % supply voltage. A traditional crystal oscillator can be replaced with this clock generator, and it would provide a stable, reliable and low temperature coefficient signal by consuming less area and cost.

    摘要 ii Abstract iii 目錄 v 圖目錄 viii 第1章 緒論 1 1.1 研究動機 1 1.2 研究目的及其應用 2 1.3 論文架構 4 第2章 非石英式振盪器及鎖相迴路簡介 5 2.1 非石英式振盪器簡介 5 2.2 非石英式振盪器架構探討 7 2.2.1 溫度補償之弛張振盪器[8][9] 7 2.2.2 具溫度補償之非石英式振盪器[3] 9 2.2.3 具電感電容振盪器之非石英式振盪器[5] 11 2.2.4 應用於生醫系統具頻率追鎖迴路之非石英式振盪器[6] 11 2.2.5 非石英式振盪器架構規格比較 13 2.3 快速鎖定鎖相迴路架構探討 14 2.3.1 基本鎖相迴路介紹 14 2.3.2 使用非線性/分段線性相位頻率偵測器之快速鎖定鎖相迴路[11][12] 16 2.3.3 使用動態相位補償技術之快速鎖定鎖相迴路[13] 18 2.3.4 可適性相位頻率偵測器之快速鎖定鎖相迴路[14] 19 2.4 本論文預期規格 21 第3章 具溫度補償技術之無參考訊號時脈產生器 23 3.1 研究動機 23 3.2 電路設計原理 23 3.2.1 非石英式振盪器[15] 24 3.2.2 溫度變異補償技術 28 3.3 模擬結果 30 第4章 快速鎖定之鎖相迴路電路介紹 35 4.1 電路架構 35 4.2 穩定度分析 37 4.3 鎖相迴路子電路介紹 41 4.3.1 數位頻帶選擇器 41 4.3.2 類比頻帶選擇器 49 4.3.3 快速鎖定相位頻率偵測器 49 4.3.4 鎖相迴路 52 第5章 晶片模擬與實作結果 65 5.1 快速鎖定鎖相迴路模擬結果 65 5.2 晶片佈局 66 5.3 量測結果 68 5.3.1 晶片照相圖 68 5.3.2 量測環境設定 69 5.3.3 鎖相迴路量測結果 71 5.3.4 無參考訊號時脈產生器之量測結果 75 5.3.5 規格比較 78 第6章 結論與未來研究方向 81 6.1 結論 81 6.2 未來研究方向 81 參考文獻 83

    [1] http://www.aecouncil.com/AECDocuments.html

    [2] Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. P. Yue, “A ±0.5 % precision on-chip frequency reference with programmable switch array for crystal-less applications” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 642-646, Oct. 2013.

    [3] F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A 65-nm CMOS temperature-compensated mobility-based frequency reference for wireless sensor networks” , IEEE J. Solid-State Circuit, vol.46, no.7, pp.1544-1552, Jul. 2011.

    [4] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A low-voltage mobility-based frequency reference for crystal-less ULP radios,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2002-2009, July. 2009.

    [5] M. S. McCorquodale, J. D. O' Day, S. M. Pernia, G. A. Carichner, S. Kubba, and R. B. Brown, "A monolithic and self-referenced RF LC clock generator compliant with USB 2.0," IEEE J. Solid-State Circuits, vol. 42, no.2, pp. 385-399, Feb. 2007.

    [6] W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y. Lee, “A frequency accuracy enhanced sub-10uW on-chip clock generator for energy efficient crystal-less wireless biotelemetry applications,” in Proc. IEEE Symp. on VLSI, pp. 115-116, 2010.

    [7] J.-C. Liu, W.-C. Lee, H.-Y. Huang, K.-H. Cheng, C.-J. Huang, Y.-W. Liang, J.-H. Peng, and Y.-H. Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in Proc. Asian Solid-State Circuits Conference, pp.117-120, 2012.

    [8] Y.-H. Chiang, and S.-I. Liu, “A submicrowatts 1.1 MHz CMOS relaxation oscillator with temperature compensation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 12, pp. 837-841, Dec. 2013.

    [9] Y.-H. Chiang, and S.-I. Liu, “Nanopower CMOS relaxation oscillator with sub-100 ppm/°C temperature coefficient,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp. 661-665, Jun. 2014.
    [10] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006.

    [11] J. Lan, F. Lai, Z. Gao, H. M. and J. W. Zhang, “A nonlinear phase frequency detector for fast-lock phase-locked loops,” IEEE 8th International Conference ASIC, pp. 1117-1120, 2009.

    [12] N. E. Seraji and M. Yavari, “Piecewise-linear phase frequency detector for fast-lock phase-locked loops,” in Proc. IEEE Int. Midwest Symposium on Circuits and System (MWSCAS), Aug. 2011.

    [13] W.-H. Chiu, Y.-H. Huang, T.-H. Lin, “A dynamic phase error compensation technique for fast-locking phase-locked loops,” IEEE J. Solid-State Circuits, vol.45, no.6, pp.1137 1148, Jun. 2010.

    [14] 李柏逸, “具數位頻帶選擇器和可適性相位頻率偵測器之快速鎖定鎖相迴路,” 碩士論文, 國立中央大學, 2013.

    [15] 葉家齊, “具溫度及電壓變異補償技術之非石英式時脈產生器,” 碩士論文, 國立中央大學, 2016.

    [16] N. Sadeghi, A. Sharif-Bakhtiar, and S. Mirabbasi, “A 0.007-mm2 108-ppm/°C 1-MHz relaxation oscillator for high-temperature application up to 108 °C in 0.13-μm CMOS,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 60, no. 7, pp. 1692-1701, Jun. 2013.

    [17] K.-J. Hsiao, “A 32.4 ppm/°C 3.2-1.6 V self-chopped relaxation oscillator with adaptive supply generation,” IEEE Symp. on VLSI, pp. 14-15, Jun. 2012.

    [18] S. M. Kashmiri, M. A. P. Pertijs, and K. A. A. Makinwa, “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1 % from - 55 °C to 125 °C,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 2510-2520, Dec. 2010.

    [19] Y. Cao, P. Leroux, W. De Cock, and M. Steyaert, “A 63,000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 402-403, Feb. 2013.

    [20] J. Lee, and S.-H. Cho, “A 10MHz 80μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS,” IEEE Symp. on VLSI, pp. 226-227, 2009.

    [21] 張啟揚, “操作在0.5伏特下具溫度補償技術非石英振盪器之全數位式時脈產生器,” 碩士論文, 國立中央大學, 2013.

    [22] Y.-C. Shih, and B. Otis, “An on-chip tunable frequency generator for crystal-less low-power WBAN radio,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 4, pp. 187-191, Mar. 2013.

    [23] R. Vijayaraghavan, S. K. Islam, M. R. Haider, and L. Zuo, “Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator,” IET Circuits, Devices & Systems, vol. 3, no. 5, pp. 259-267, Oct. 2009.

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