在現今機器視覺系統多以SoC嵌入式軟硬體整合方法設計，使用FPGA取代多個DSP模組。在傳統的開發中，通常依據需求先設計軟體雛型，接著再將某些模組硬體化，達成軟硬體共同設計之系統。硬體模組多以連續串流進行設計，然而這種方法較缺乏彈性，當需求只要小小改變時，整個硬體模組可能就不適用需要重新規劃。
本論文提出嵌入式視覺軟硬體設計方法論，以IDEF0進行系統分析，將需求階層式模組化切割為多個子模組，再以Grafcet建立各個子模組的離散事件模型，透過快速對應產生軟體語言及硬體語言，此方法論的優點是開發者在系統開發前期不需撰寫程式。另外本論文提出硬體介面控制器，針對軟硬體共同設計之平台，在開發者針對不同目標需求(效能、彈性、成本、耗電)選用硬體模組時，不必重新規劃硬體模組間的設計，只需要透過軟體控制即可規劃硬體模組執行之順序，增加硬體模組之開發彈性，加快系統開發流程。

In recent years, most of the machine vision systems use embedded hardware and software co-design, which uses FPGA to replace some DSP modules. In traditional development, we first design software prototype and then choose some modules that designed by hardware. We use a series designed to connect this hardware modules to compose hardware architecture. However, this type of architecture lacks flexibility. If system requirements just need to do a little change, the architecture need to whole redesign.
In this thesis, we propose embedded vision hardware and software co-design methodology. Firstly, we analyze the system requirements with IDEF0. This way is analysis whole system hierarchically and divided into many modules. Secondly, we use Grafcet establish discrete event model for every modules. Then we through the way of Grafcet synthesis to produce software code and hardware design. This development approach needs not coding in prophase of system design. Additionally, we design a hardware interface controller, which is suitable in hardware and software co-design architecture. This controller contains all of hardware modules, and designers can select desired target modules according to system requirements which include efficacy, elasticity, cost, and power consumption. It is not necessary to redesign hardware architecture, the designer just to change the order of hardware modules through software. The hardware interface controller can increased development flexibility, and accelerate the system development process.

[1] D. Braggins, "Vision for industry [Auotmation]," Engineering & Technology, vol. 3, pp. 48-50, 2008.
[2] K. T. Tseng, W. F. Huang and C.H. Wu, "Vision-based finger guessing game in Human Machine Interaction," IEEE International Conference on Robotics and Biomimetics, pp. 619-624, 2006.
[3] [Online.] Microsoft Xbox website, "Kinect for Xbox 360," "http://www.xbox.com/zh-TW/kinect"
[4] [Online.] Leap motion website, "The leap motion controller,"
"https://www.leapmotion.com/"
[5] M. Hofstatter, M. Litzenberger, D. Matolin and C. Posch, "Hardware-accelerated address-event processing for high-speed visual object recognition," IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 89-92, 2011.
[6] [Online.] National Instruments website, " National Instruments," "http://taiwan.ni.com"
[7] C. H. Gebotys and R. J. Gebotys, " Complexities in DSP software compilation: performance, code size, power, retargetability," Proceedings of the Thirty-First Hawaii International Conference on System Sciences, vol. 3, pp. 150-156, 1998.
[8] S. M. H. Ho, S. C. L. Yuen, C. P. Hiu, T. C. P. Chau, A. Yan-Qing, P. H. W. Leong, O. C. S. Choy and P. Kong-Pang, "Structured ASIC: Methodology and comparison," International Conference on Field-Programmable Technology (FPT), pp. 377-380, 2010.
[9] J. Forrest and S. Wright, "The cosynthesis of C using assembly extraction," IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems, pp. 3/1-3/5, 1996.
[10] M. Edwards and P. Green, "An object oriented design method for reconfigurable computing systems," Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 692-696, 2000.
[11] S. Chakraverty, "Cosynthesis of multiprocessor architectures with high availability," International Conference on VLSI Design, pp. 927-932, 2004.
[12] L. Debowski, "A flexible DSP/FPGA-based hardware platform for power electronics," Signal Processing Algorithms, Architectures, Arrangements, and Applications Conference Proceedings (SPA), pp. 30-35, 2009.
[13] A. Mohsen and R. Hofmann, "Characterizing power consumption and delay of functional/library components for hardware/software co-design of embedded systems," IEEE Internation Workshop on Rapid System Prototyping, pp. 45-52, 2004.
[14] M. Theissinger, P. Stravers and H. Veit, "Castle: An Interactive Environment for HW-SW CO-Design," Proceedings of the Third International Workshop on Hardware/Software Codesign, pp. 203-209, 1994.
[15] C. Carreras, J. C. Lopez, M. L. Lopez, C. Delgado-Kloos, N. Martinez and L. Sanchez, "A CO-Design Methodology Based on Formal Specification and High-level Estimation," International Workshop on Hardware/Software Co-Design, pp. 28-35, 1996.
[16] G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels and I. Bolsens, "Hardware/software partitioning of embedded system in OCAPI-xl," Proceedings of the Ninth International Symposium on Hardware/Software Codesign, pp. 30-35, 2001.
[17] J. T. Olson, J. W. Rozenblit, C. Talarico and W. Jacak, "Hardware/Software Partitioning Using Bayesian Belief Networks," IEEE Transactions on Systems, Man and Cybernetics, Part A: Systems and Humans, vol. 37, pp. 655-668, 2007.
[18] F. K. a. Luqi, "An Introduction to Rapid System Prototyping," IEEE Transactions on Software Engineering, vol. 28, pp. 817 - 821, Sep 2002.
[19] I. Bravo, A. Hernández, A. Gardel, R. Mateos, J. L. Lazaro and V. Diaz, "Different Proposals To The Multiplication of 3x3 Vision Mask In VHDL For FPGA's," IEEE Conference Emerging Technologies and Factory Automation, vol. 2, pp. 208-211, 2003.
[20] J. Velten and A. Kummert, "FPGA-based Implementation of variable sized structuring elements for 2D binary morphological operations," IEEE International Workshop on Electronic Design, Test and Applications, pp. 309-312, 2002.
[21] M. S. Hamid and S. Marshall, "FPGA Realisation of the Genetic Algorithm for the Design of Grey-Scale Soft Morphological Filters," International Conference on Visual Information Engineering, pp. 141-144, 2003.
[22] C. H. Huang, "An FPGA-based Point Target Detection System using Morphological Clutter Elimination," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2436-2439, 2013.
[23] K. Haris, S. N. Efstratiadis, N. Maglaveras and A. K. Katsaggelos, "Hybrid image segmentation using watersheds and fast region merging," IEEE Transactions on Image Processing, vol. 7, pp. 1684-1699, 1998.
[24] C. J. Kuo, S. F. Odeh and M.C. Huang, "Image Segmentation With Improved Watershed Algorithm And Its FPGA Implementation," IEEE International Symposium on Circuits and Systems, vol. 2, pp. 753-756, 2001.
[25] C. Rambabu, T. S. Rathore and I. Chakrabarti, "A New Watershed Algorithm Based on Hillclimbing Technique for Image Segmentation," Conference on Convergent Technologies for the Asia-Pacific Region, vol. 4, pp. 1404-1408, 2003.
[26] T. Kryjak, M. Komorkiewicz and M. Gorgon, "Hardware Implementation of the PBAS Foreground Detection Method in FPGA," International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 479-484, 2013.
[27] N. Otsu, "A threshold selection method from gray-level histograms," IEEE Transactions on Systems, Man and Cybernetics, vol. 9, pp. 62-66, 1979.
[28] C. H. Chen, T. K. Yao, J. H. Dai and C. Y. Chen, "A pipelined multiprocessor SOC design methodology for streaming signal processing," Journal of Vibration and Control, vol. 20, pp. 163-178, 2014.
[29] C. H. Chen, C. M. Kuo, C. Y. Chen, and J. H. Dai, "The design and synthesis using hierarchical robotic discrete-event modeling," Journal of Vibration and Control, vol.19, pp. 1603-1613, 2013.
[30] R. J. Mayer, "IDEF0 Function Modeling," Air force Systems Command, 1992.
[31] [Online.] IEC website, " International Electrotechnical Commission," "http://www.iec.ch"
[32] K. Kim, T. H. Chalidabhongse, D. Harwood, and L. Davis, "Real-time foreground-background segmentation using codebook model," Real-Time Imaging, vol. 11, pp. 172-185, 2005.
[33] [Online.] Xilinx website, "Xilinx XUP ZedBoard," "http://www.xilinx.com/support/university/boards-portfolio/xup-boards/XUPZedBoard.html"
[34] 陳柏瑞, "一個快速立體視覺系統的嵌入式硬體設計," 國立中央大學資訊工程學系碩士論文, 2010.