隨著電晶體尺寸下降，且製程微縮至90 奈米以下，會帶來較劇烈的參數變動。 在未來SoC 設計時，類比EDA 的需求越來越重要。在晶圓廠製造過程中，因為經過相同的物理程序，所以電晶體間的參數變動會有某種程度的關聯性，此關聯性可用來改善良率。在本論文中，建構一個類比電路設計自動化異質平台，以MATLAB所架構，並整合了數種不同環境，包含了電路模擬器(Hspice), 工作站作業系統連線通訊協定(SSH)與檔案傳輸協定(Ftp)，並以一個雙級運算放大器為範例，根據兩步驟的最佳化程序，考量空間相關性來決定佈局時電晶體最佳的佈局擺放位置。由模擬結果得知，本平台可找到對不同規格之最佳排法，有效地提升良率。

While MOS transistors continuously scale down in technologies below 90 nano-meter, they bring along larger parameter variability. Analog EDA is needed increasingly
important in future SoC design. The parameter variation of all transistors should have certain correlations during IC manufacturing process because all of them are made from the common physical process and the correlations can be used for yield improvement. In this thesis, a heterogeneous platform of analog EDA, which is implemented on MATLAB, is provided by integration of several environments including the circuit simulator (Hspice), communication protocol via workstation OS (SSH) and file transfer protocol (Ftp). A two-stage OpAmp is used as an example circuit to demonstrate the performance of a proposed two-step optimization procedure for determination of best layout placement by spatial correlation. By the simulation results, the best layout placements with respect to the corresponding parameters can be given to improve the effective yield.

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