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研究生： 胡嘉琳
Chia-Lin Hu
論文名稱： 應用於ATSC VSB時脈回復之全數位延遲線迴路
All Digital DLL for ATSC VSB Timing Recovery
指導教授： 蘇朝琴
Chauchin Su
口試委員:
學位類別： 碩士
Master
系所名稱： 資訊電機學院 - 電機工程學系
Department of Electrical Engineering
畢業學年度： 89
語文別： 中文
論文頁數： 77
中文關鍵詞： 延遲線迴路 、時脈回復
外文關鍵詞： DLL, Timing Recovery
相關次數： 點閱：11  下載：0 
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    • 我們透過C和Verilog的模擬驗證其可行性，且使用TSMC 0.35μm 1P4M的製成實現整個硬體架構。整個電路只使用了近3000個邏輯閘，晶片面積為524μm×517μm (不包含I/O 單元) 。晶片測試結果也符合規格的要求，其所能產生之相位解析度為370ps至810ps之間，時脈所產生之抖動在270ps之內。


    We use C language and Verilog language to simulate the architecture and verify the functionality. Then, the chip had been designed and implemented using TSMC 0.35μm 1P4M technology. The gate count of 3000 reconfirms the simplicity of the architecture. The area of the chip is 524μm×517μm (not including I/O pad). Finally, the test result fits the required specification It products a phase resolution between 370ps to 810ps, and the clock jitter is lower than 270

    Chapter 1Introduction 1.1Overview 1.2Introduction of ATSC HDTV System 1.3Survey of the Timing Recovery Architecture 1.4Motivation 1.5Introduction of DLL 1.6Survey of the Delay Locked Loop 1.7Thesis Organization Chapter 2 Architecture 2.1Overview 2.2Tap Delay Line , Switch, and Multiplexer 2.3Lead/Lag Detection 2.4Align_state Block 2.5Pasecomp_state Block Chapter 3 Design Considerations 3.1Phase resolution 3.2Analyze the phase resolution 3.3The relationship between phase resolution and confidence counter 3.4The clock jitter propagation Chapter 4Implementation and simulation result 4.1C program simulation result 4.2Verilog simulation result 4.3Design Analyzer simulation result 4.4Chip Implementation 4.5Post layout simulation result Chapter 5Test consideration and result 5.1Test consideration 5.2Test method 5.3Test result Chapter 6The application of DLL on ATSC HDTV timing recovery 6.1Overview 6.2C program simulation and result Chapter 7Conclusion Bibliography

    [1]Advanced Television System Committee, ATSC Digital Television Standards, Sept. 1995.
    [2]Advanced Television System Committee, Guide to the use of ATSC Digital Television Standards, Oct. 1995.
    [3]Gary Sgrignili, Wayne Bretl, and Richard Citta, “VSB Modulation Used for Terrestrial and Cable Broadcasts”, IEEE Trans. On Consumer Electronics, Vol. 42, No. 3, Aug. 1995, pp.367-382.
    [4]Kim, Shin, and Song, “A Symbol Timing Recovery Using the Segment Sync Data for the Digital HDTV GA VSB System”, IEEE Tran. On Consumer Electronics, Vol. 42, No. 3, August 1996, pp.651-656.
    [5]C.C. Su, L.Y. Huang, J.J. Lee, and C.K. Wang, “A Frame-Based Symbol Timing Recovery for Large Pull-in Rang and Small Steady Sate Variation,” Proc. 1999 Asia Pacific Conference on ASICs, 1999, pp. 75-78.
    [6]Ting-Yuan Cheng, “Immediately Frequency and Phase Error Compensation Technique for the Frame Based Timing Recovery”, Master Thesis, NCU Department of Electrical EngineeringNational Central UniversityChung-Li, ROC, 1999.
    [7]Roland E. Best, “Phase-Locked Loops: Theory, Design, and Applications”, McGraw-Hill Inc., 2nd ed., 1993.
    [8]Stefnos Sidiropouls, and Mark A, Horowits, “A Semidigital Dual Delay-Locked Loop”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 32, NO. 11, November 1997, pp. 1683-1692.
    [9]Bruno W. Garlepp, Kevin S. Donnely, et al., “A Portable Digital DLL for High-Speed CMOS Interface Circuits”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 34, NO. 5, MAY 1999, pp. 632-644.
    [10]Thomas H. Lee, Kevin S, Donnelly, John T. C. Ho, Jared Zerbe, Mark G. Johnson, and Toru Ishikawa, “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 29, NO. 12, December 1994, pp.1491-1496.

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